cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 216

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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GLPCI_SB Register Descriptions
5.2.1.4
MSR Address
Type
Reset Value
The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 1. Reading the FLAG bit returns
the value; writing 1 clears the flag; writing 0 has no effect. (See Section 3.8.4 "MSR Address 3: Error Control" on page 71
for further details.)
63:23
15:7
Bit
22
21
20
19
18
17
16
6
5
4
3
2
1
0
GeodeLink Device Error MSR (GLPCI_GLD_MSR_ERROR)
Name
RSVD (RO)
TAS_ASMI_
FLAG
PAR_ASMI_
FLAG
SYSE_ASMI_
FLAG
EXCEP_ASMI_
FLAG
SSMI_ASMI_
FLAG
TAR_ASMI_
FLAG
MAR_ASMI_
FLAG
RSVD (RO)
TAS_ASMI_EN
PAR_ASMI_EN
SYSE_ASMI_
EN
EXCEP_ASMI_
EN
SSMI_EN
TAR_ASMI_EN
MAR_ASMI_EN
51000003h
R/W
00000000_00000000h
Description
Reserved (Read Only). Returns 0.
Target Abort Signaled ASMI Flag. If high, records that an ASMI was generated due the
signaling of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect.
TA_ASMI_EN (bit 6) must be high to generate ASMI and set flag.
Parity Error ASMI Flag. If high, records that an ASMI was generated due to the detec-
tion of a PCI bus parity error. Write 1 to clear; writing 0 has no effect. PAR_ASMI_EN (bit
5) must be high to generate ASMI and set flag.
System Error ASMI Flag. If high, records that an ASMI was generated due to the detec-
tion of a PCI bus system error. Write 1 to clear; writing 0 has no effect. SYSE_ASMI_EN
(bit 4) must be high to generate ASMI and set flag.
Exception Bit Flag. If high, records that an ASMI was generated due to the EXCEP bit
being set in the received GLIU read or write response packet. Write 1 to clear; writing 0
has no effect. EXCEP_ASMI_EN (bit 3) must be set to enable this flag.
SSMI ASMI Flag. If high, records that an ASMI was generated due to the SSMI bit being
set in the received GLIU read or write response packet. Write 1 to clear; writing 0 has no
effect. SSMI_ASMI_EN (bit 2) must be set to enable this flag.
Target Abort Received ASMI Flag. If high, records that an ASMI was generated due to
the reception of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect.
TAR_ASMI_EN (bit 1) must be high to generate ASMI and set flag.
Master Abort Received ASMI Flag. If high, records that an ASMI was generated due to
the reception of a master abort on the PCI bus. Write 1 to clear; writing 0 has no effect.
MAR_ASMI_EN (bit 0) be high to generate ASMI and set flag.
Reserved (Read Only). Returns 0.
Target Abort Signaled ASMI Enable. Write 1 to enable TAS_ASMI_FLAG (bit 22) and
to allow the event to generate an ASMI.
Parity Error ASMI Enable. Write 1 to enable PAR_ASMI_FLAG (bit 21) and to allow the
event to generate an ASMI.
System Error SMI Enable. Write 1 to enable SYSE_ASMI_FLAG (bit 20) and to allow
the event to generate an ASMI.
Exception Bit Enable. Write 1 to enable EXCEP_ASMI_FLAG (bit 19) and to allow the
event.
SSMI Enable. Write 1 to enable SSMI_ASMI_FLAG bit (bit 18) and to allow the event.
Target Abort Received ASMI Enable. Write 1 to enable TAR_ASMI_FLAG (bit 17) and
to allow the event to generate an ASMI.
Master Abort Received ASMI Enable. Write 1 to enable MAR_ASMI_FLAG (bit 16) and
to allow the event to generate an ASMI.
GLPCI_GLD_MSR_SMI Bit Descriptions
(Continued)
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Revision 0.8