cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 58

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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Global Concepts and Features
3.5.2
Each of the clock domains listed in Table 3-3 is subject to
various GLCP controls and status registers except those
with “Note 3”. These registers and a brief description of
each is provided:
• GLCP Clock Active (GLCP_CLKACTIVE), MSR
• GLCP Clock Control (GLCP_CLKOFF), MSR
• GLCP Clock Mask for Debug Clock Stop Action
• GLCP Clock Active Mask for Suspend Acknowledge
• GLCP Clock Mask for Sleep Request
All of the registers above have the same layout, where
each bit is associated with a clock domain. The layout and
recommended operating values for the registers is pro-
vided in Table 5-73 "Clock Mapping / Operational Settings"
on page 518.
3.5.2.1
• GLCP Debug Clock Control (GLCP_DBGCLKCTL),
• GLCP Global Power Management Control
• GLCP Clock Disable Delay Value
51700011h: A 1 indicates the corresponding clock is
active. This is a read only register.
51700010h: A 1 indicates the corresponding clock is to
be disabled immediately and unconditionally. Not
normally used operationally. Debug only.
(GLCP_CLKDISABLE), MSR 51700012h: A 1 indicates
the corresponding clock is to be disabled by debug logic
via a debug event or trigger. Not normally used opera-
tionally. Debug only.
(GLCP_CLK4ACK), MSR 51700013h: A 1 indicates the
corresponding clock is to be monitored during a power
management Sleep operation. When all the clocks with
associated 1s go inactive, the GLCP sends a Sleep
Acknowledge to the Power Management Controller. This
register is used during Sleep sequences and requires
the CLK_DLY_EN bit in GLCP_GLB_PM (MSR
5170000Bh[1]) to be 0.
(GLCP_PMCLKDISABLE), MSR 51700009h: A 1 indi-
cates the corresponding clock is to be disabled uncondi-
tionally during a power management Sleep operation.
Clocks are disabled when the GLCP completes all of its
Sleep Request operations and sends a Sleep Acknowl-
edge to the Power Management Controller.
MSR 51700016h: Set all bits to 0. This turns off all
clocks to debug features; not needed during normal
operation.
(GLCP_GLB_PM), MSR 5170000Bh: Set all bits to 0.
This disables the use of the fixed delay in
GLCP_CLK_DIS_DELAY and enables the use of
GLCP_CLK4ACK.
(GLCP_CLK_DIS_DELAY), MSR 51700008h: Set all
bits to 0. Since use of this register is disabled by setting
all GLCP_DBGCLKCTL bits to 0, the actual value of this
register is a “don’t care”; it is set here for completeness.
If use of GLCP_CLK_DIS_DELAY is desired, set the
CLK_DLY_EN bit in GLCP_GLB_PM (MSR
Clock Controls and Setup
Additional Setup Operations
(Continued)
58
3.6
The elements that effect “reset” within the CS5535 are
illustrated in Figure 3-6 on page 59. The following points
are significant:
• Signals denoted in upper case (i.e., all capitals) are
• There are separate resets for the Working power domain
• All elements in the figure are within the Standby power
• The TAP Controller is in the Working power domain, but
• Any time the CS5535 is in the Standby state, the
• Any faulted event or external reset input forces the
• External reset (RESET_OUT#) is always asserted
• IDE_RESET# is always asserted immediately with
• LVD monitors V
• LVD monitors V
When power is applied to the CS5535 from a completely
cold start, that is, no Standby or Working power, both
RESET_STAND# and RESET_WORK# are applied. Alter-
natively, one or both of the reset inputs may be tied to
Standby I/O power (V
erate internal Power Good Working and internal Power
Good Standby. Assuming the LVD circuit is enabled
(LVD_EN# pin tied low), Power Good Standby will assert
until proper Standby voltages have been achieved and
RESET_STAND# has been de-asserted.
5170000Bh[1] = 1). This will disable the use of
GLCP_CLK4ACK and shut off the clocks in
GLCP_PMCLKDISABLE after the
GLCP_CLK_DIS_DELAY expires. This delay is
measured in PCI clock edges.
external pins. Signals denoted in lower case are internal
signals.
(RESET_WORK#) and the Standby power domain
(RESET_STAND#).
domain and operate off the KHZ32_CLK.
it may be reset separately from the other Working
domain logic.
Working power domain is unconditionally and immedi-
ately driven into reset.
CS5535 into the Standby state.
immediately with internal working domain reset but is
de-asserted subject to a programmable delay.
RESET_OUT# asserts without any clocks but requires
the KHZ32_CLK for the delay and the PCI_CLK to de-
assert.
internal working domain reset and de-asserts when the
ATAC comes out of reset, that is, within a few
MHZ66_CLK edges of internal reset de-assert.
power_good_working when V
operating range.
RESET_STAND#. The assertion of power_good_standy
only occurs when the voltages are within normal oper-
ating range and RESET_STAND# is high, that is, de-
asserted.
RESET CONSIDERATIONS
CORE
CORE_VSB
IO_VSB
and only asserts
), and the LVD circuit will gen-
and V
CORE
IO_VSB
is within normal
along with
Revision 0.8