lpc4310 NXP Semiconductors, lpc4310 Datasheet - Page 2

• Manufacturer Part Number: lpc4310
• Description: Lpc4350/30/20/10 32-bit Arm Cortex-m4/m0 Mcu; Up To 264 Kb Sram; Ethernet; Two High-speed Usbs; Advanced Configurable Peripherals
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC4350_30_20_10
Objective data sheet
Configurable digital peripherals
Serial interfaces
Digital peripherals
32 bit One-Time Programmable (OTP) memory for customer use.
Serial GPIO (SGPIO) interface.
State Configurable Timer (SCT) subsystem on AHB.
Quad SPI Flash Interface (SPIFI) with four lanes and up to 40 MB per second.
10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load.
One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip high-speed PHY.
One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY.
One 550 UART with DMA support and full modem interface.
Three 550 USARTs with DMA and synchronous mode support and a smart card
interface conforming to ISO7816 specification. One USART with IrDA interface.
One C_CAN 2.0B controller with one channel.
Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
One SPI controller.
One Fast-mode Plus I
pins conforming to the full I
1 Mbit/s.
One Fast-mode I
Two I
External Memory Controller (EMC) supporting external SRAM, ROM, flash, and
SDRAM devices.
LCD controller with dedicated DMA controller and a selectable display resolution of
up to 1024 × 768 pixels. Supports monochrome, Super-Twisted Nematic (STN),
and Thin-Film Transistor (TFT) panels; supports up to 24-bit true-color mode.
Secure Digital Input Output (SDIO) card interface.
Eight-channel General-Purpose DMA (GPDMA) controller can access all memories
on the AHB and all DMA-capable AHB slaves.
Up to 146 General-Purpose Input/Output (GPIO) pins with configurable
pull-up/pull-down resistors and open-drain modes.
GPIO registers are located on the AHB for fast access. GPIO ports have DMA
support.
Four general-purpose timer/counters with capture and match capabilities.
One motor control Pulse Width Modulator (PWM) for three-phase motor control.
One Quadrature Encoder Interface (QEI).
Repetitive Interrupt timer (RI timer).
Windowed watchdog timer (WWDT).
Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes
of battery powered backup registers.
Alarm timer; can be battery powered.
2
S interfaces, each with DMA support and with one input and one output.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 October 2010
2
C-bus interface with monitor mode and with standard I/O pins.
2
C-bus interface with monitor mode and with open-drain I/O
2
C-bus specification. Supports data rates of up to
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
© NXP B.V. 2010. All rights reserved.
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