lpc4310 NXP Semiconductors, lpc4310 Datasheet - Page 43

• Manufacturer Part Number: lpc4310
• Description: Lpc4350/30/20/10 32-bit Arm Cortex-m4/m0 Mcu; Up To 264 Kb Sram; Ethernet; Two High-speed Usbs; Advanced Configurable Peripherals
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC4350_30_20_10
Objective data sheet
7.13.6.1 Features
7.13.7.1 Features
7.13.6 I
7.13.7 C_CAN
The I
The I
and one word select signal. The basic I
always the master, and one slave. The I
receive channel, each of which can operate as either a master or a slave.
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a very high level of security.
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S0/1 interfaces
Both I
master or slave mode.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48,
96) kHz.
Support for an audio master clock.
Configurable word select period in master mode (separately for I
output).
Two 8-word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests for each I
These are connected to the GPDMA block.
Controls include reset, stop and mute options separately for I
output.
Conforms to protocol version 2.0 parts A and B.
Supports bit rate of up to 1 Mbit/s.
Supports 32 Message Objects.
Each Message Object has its own identifier mask.
Provides programmable FIFO mode (concatenation of Message Objects).
Provides maskable interrupts.
Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.
Provides programmable loop-back mode for self-test operation.
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S-bus provides a standard communication interface for digital audio applications.
S-bus specification defines a 3-wire serial bus using one data line, one clock line,
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S interfaces have separate input/output channels, each of which can operate in
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 October 2010
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S interface, controlled by programmable buffer levels.
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S-bus connection has one master, which is
S-bus interface provides a separate transmit and
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
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S-bus input and I
2
S-bus input and
© NXP B.V. 2010. All rights reserved.
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S-bus