pxb4219 Infineon Technologies Corporation, pxb4219 Datasheet - Page 12

• Manufacturer Part Number: pxb4219
• Description: Iwe8 Interworking Element For 8 E1/t1 Lines
• Manufacturer: Infineon Technologies Corporation

List of Figures
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Data Sheet
I.432.3) 50
(excluding the HEC field) (Table 1/I.361) 53
Up 70
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Typical IWE8 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Line Card for 8 T1/E1 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Echo Canceller Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Cell delineation state diagram (Figure 5/I.432.1) . . . . . . . . . . . . . . . . . 50
Maintenance state transition diagram for cell delineation events (Figure 2/
HEC: Receiver mode of Operation (Figure 3/ITU I.432.1) . . . . . . . . . . 51
HEC Detection According to ATM Forum . . . . . . . . . . . . . . . . . . . . . . 52
Pre-assigned cell header values at the UNI for use by the physical layer
Pre-defined header field values [11] . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SAR-PDU of AAL Type 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Synchronization of SRTS Generation with the Start of Segmentation . 60
Reassembly Buffer Initialization: No CDV . . . . . . . . . . . . . . . . . . . . . . 67
Reassembly Buffer Initialization: positive CDV at Start Up . . . . . . . . . 68
Reassembly Buffer Initialization: Negative CDV at Start Up . . . . . . . . 69
Reassembly Buffer Initialization for structured CES: positive CDV at Start
Block Diagram of the ICRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Transient Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Influence of Damping on Lock in Time. . . . . . . . . . . . . . . . . . . . . . . . . 79
Connection of IWE8 to QuadFALC . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Framer Interface in FAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Framer Interface in GIM T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Framer Interface in GIM E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Framer Interface in SYM2 E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Framer Interface in SYM8 E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Framer Interface in EC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
UTOPIA Receive and Transmit Interfaces in Slave Mode . . . . . . . . . 107
Utopia Sideband Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
IMA Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Connection of IWE8 to an Intel Type Microprocessor . . . . . . . . . . . . 115
Connection of IWE8 to an Motorola Type Microprocessor . . . . . . . . 116
External RAM Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
RAM Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Clock Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
ACM Jitter Tolerance in E1 Mode without Jitter Attenuator . . . . . . . . 230
Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Structure of the IWE8 external RAM . . . . . . . . . . . . . . . . . . . . . . . . . 137
12
PXB4219 / PXB4220 / PXB4221
2002-05-06
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