pxb4219 Infineon Technologies Corporation, pxb4219 Datasheet - Page 28

• Manufacturer Part Number: pxb4219
• Description: Iwe8 Interworking Element For 8 E1/t1 Lines
• Manufacturer: Infineon Technologies Corporation

Table 2
Pin No.
V10
V13
W13
V4, U5, Y3,
Y4, V5
Y6, V7,
W7, Y7,
V8, W8,
Y8, U9
V9
W6
Data Sheet
Symbol
RXCLAV
RXCLK
RXENB
RXADR[4:0]
TXDAT[7:0]
TXPTY
TXSOC
UTOPIA Interface (36 pins) (cont’d)
Input (I)
Output (O)
Slave: O
Master: I
PDA
I
Slave: I
Master: O
PUA
I
PUA
I
PUA
I
PUA
I
PDA
28
Function
UTOPIA Receive Cell Available
Slave: RXCLAV is an active high signal
asserted by the PHY layer to indicate that it
has data available for transfer to the ATM
layer.
Master: RXCLAV is an active high signal
asserted by the ATM layer to indicate that it
has data available for transfer to the PHY
layer.
UTOPIA Receive Clock
Transfer/synchronization clock from the
ATM layer to the PHY layer for
synchronizing transfers on RXDAT[0:7].
UTOPIA Receive Enable
Slave: Active low signal asserted by the
ATM layer to indicate that RXDAT[0:7] and
RXSOC will be sampled at the end of the
next cycle.
Master: Active low signal asserted by the
PHY layer to indicate that RXDAT[0:7] and
RXSOC will be sampled at the end of the
next cycle.
UTOPIA Receive Address Bus
Five bit wide true data driven from the ATM
to MPHY layer to select the appropriate
MPHY device. RXADR[4] is the MSB.
UTOPIA Transmit Data Bus
Byte-wide true data driven from ATM to
PHY layer. TXDAT[7] is the MSB.
UTOPIA Transmit Odd Parity Bit
TXPTY is the odd parity bit over TXDAT[0:7]
driven by the ATM layer.
UTOPIA Transmit Start-of-Cell
Active high signal asserted by the ATM
layer when TXDAT[0:7] contains the first
valid byte of the cell.
PXB4219 / PXB4220 / PXB4221
Pin Descriptions
2002-05-06