pxb4219 Infineon Technologies Corporation, pxb4219 Datasheet - Page 131

• Manufacturer Part Number: pxb4219
• Description: Iwe8 Interworking Element For 8 E1/t1 Lines
• Manufacturer: Infineon Technologies Corporation

sdt_once
crv_en
mcp_reinit
aal0
part_fill
band_width
sdt
Data Sheet
1 =
SDT pointer appears once in 8 cell cycle
X =
0 =
1 =
Data to Clock Recovery interface enable (RTS values and/or ACM buffer
filling levels) This bit may only be set for one channel per port.
X =
0 =
1 =
Only one channel per port may have crv_en set to 1.
Microprocessor forced reassembly buffer reinitialization
The SW should set and reset this bit to continue proper operation.
0 =
1 =
AAL0 enable
0 =
1 =
Partially filled cell filling level
4 to
48
4 to
47
4 to
47
4+Cb
to 47
band_width
N
X =
Structured Data Transfer enable
If [aal0] = 1 or [sdt] = 0
if (pcfN[p_srts] = 0 and pcfN[p_acm] = 0) or acfg[a_crv_en] = 0
if pcfN[p_ces] = 1
Enabled
All cells with CSI bit = 1 and even SN are supposed to contain a
P format SAR-SDU.
Only the first cell with CSI bit = 1 and even SN in a cycle of 8 cells
is supposed to contain a P format SAR-SDU. (recommended for
SDT)
Disabled
Enabled
Disabled
Enabled
Disabled (AAL1 is used)
Enabled (instead of AAL1)
AAL0:
[aal0] = 1
AAL1 unstructured CES:
[aal0] = 0, pcfN[p_ces] = 1
AAL1 structured CES without CAS
[aal0] = 0, pcfN[p_ces] = 0, pcfN[p_cas] = 0
AAL1 structured CES with CAS
[aal0] = 0, pcfN[p_ces] = 0, pcfN[p_cas] = 1
(with N = number of timeslots for this channel)
131
PXB4219 / PXB4220 / PXB4221
2)
:
1)
:
Memory Structure
2002-05-06