pxb4219 Infineon Technologies Corporation, pxb4219 Datasheet - Page 79

• Manufacturer Part Number: pxb4219
• Description: Iwe8 Interworking Element For 8 E1/t1 Lines
• Manufacturer: Infineon Technologies Corporation

The tuning range of the DCO is limited to the value programmed to bits “tur” in register
“condN”. If the phase detector requests a higher frequency deviation the DCO enters
out-of-range condition. In this case the DCO’s output will be clipped and bit “max” of
register “statN” will be set. If the number of out-of-range conditions during 16 ATM cells
exceeds the value given by field “tr_acm” of register “treshN”, an out-of-lock message,
indicated via field “ola” of register “oolN”, is generated.
Increasing the loop-gain reduces the damping of the PLL-ACM. This will reduce the rise
time but results in overshoot and long lock-in times.
Reducing the loop-gain increases the damping. This results in lower cut off frequencies,
and prevents overshoot. Thus, CDV is less likely to drive the PLL out of lock. The rise
and lock-in time are increased. If the loop-gain is too low, the amount of bytes required
to drive the DCO over it's tuning range could cause a data buffer over- or underflow.
Optimized damping allows minimum lock-in time without overshoot. In this case PLL-
ACM’s frequency is moving asymptotically to the correct value.
Figure 21
PLL-ACM tries to keep the number of bytes in the Reassembly Buffer at the average
buffer filling value programmed to register “avbN”. This value should be equivalent to the
number of bytes stored in the Reassembly Buffer during start-up, as defined by the value
programmed in the “starv_ini” field of the “AAL Transmit Reference Slot” in RAM3.
Data Sheet
f/f
1
0.1
0
Influence of Damping on Lock in Time
Tr(dl)
Tr(do) = Tl(do)
do
dh
dl
79
dl: low damping
dh: high damping
do: optimized damping
PXB4219 / PXB4220 / PXB4221
Tr(dh) = Tl(dh)
Operational Description
t
2002-05-06