pxb4219 Infineon Technologies Corporation, pxb4219 Datasheet - Page 121

• Manufacturer Part Number: pxb4219
• Description: Iwe8 Interworking Element For 8 E1/t1 Lines
• Manufacturer: Infineon Technologies Corporation

6.1
The 4 internal 256 x 32 bit configuration RAM’s (RAM1, RAM2, RAM3 and RAM4) are
used to assign the timeslots of the Framer Receive and Framer Transmit interfaces to
ATM channels. For each port there are 32 entries. RAM1 is used to define the timeslots
of the Framer Receive ports, and RAM2 and RAM3 are used to define the Framer
Transmit ports. RAM4 is responsible for CAS conditioning and freezing in transmit
direction
When the contents of the internal RAMs have been altered by the software, the internal
state machines will load the new values within the next 1.5 frame cycles (187.5 µs). Up
to that point of time the previous values are used.
6.1.1
Read/write Address 00200
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size 256K × 32 bits: 8 ports x 32 slots x 1 doubleword
MPADR
6.1.1.1
Read/write Address 00200
Reset value: Not applicable. RAM must be reset and initialized via SW.
Data Sheet
ocd_start
_intrpt
31
23
15
7
17 16 15 14 13 12 11 10 9
Internal Configuration RAM’s
RAM1: Receive Port Configuration
0
RAM1: ATM Receive Reference Slot
ocd_end
_intrpt
0
0
go_hunt
0
H
0
H
to 003FF
to 003FF
0
idle_cells
delete_
0
Not used
Not used
Not used
H
H
0
121
descram
1
x43_
bling
8
port_nr
PXB4219 / PXB4220 / PXB4221
[2:0]
7
channel_mode[1:0]
6
5
4
slot[4:0]
Memory Structure
3
2
2002-05-06
ref_slot
1
= 1
24
16
8
0
0