m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 103

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Operation
Note
2.5.2 Operation of Serial Interface Special Function (transmission in master mode
In transmitting data in serial interface special function master mode, choose functions from those listed in
Table 2.5.1. Operations of the circled items are described below. Figure 2.5.8 shows the operation timing,
and Figures 2.5.9 and 2.5.10 show the set-up procedures.
without delay)
Table 2.5.1. Choosed functions
(1) Set an SS port of the receiver side IC to output "L" level.
(2) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit
(3) In synchronization with the first falling edge of the transfer clock, transmission data held in the
(4) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”,
(5) If the next transmission data is set in the UARTi transmit buffer register while transmission is
• Set SSi pin to "H" level. If "L" level is input to the pin, a fault error will be generated.
CLK polarity
Transfer clock
source
Transmission
interrupt factor
buffer register makes data transmissible status ready.
UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the
UARTi transmit interrupt request bit goes to “1”. Also, the first bit of the transmission data is
transmitted from the TxDi pin. Then the data is transmitted bit by bit from the lower order in
synchronization with the falling edges.
which indicates that transmission is completed. The transfer clock stops at “L” level.
in progress (before the eighth bit has been transmitted), the data is transmitted in succession.
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Item
Item
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O
O
O
Transmission buffer empty
Transmission complete
Internal clock (f
External clock (CLKi pin)
Output transmission data at
the falling edge of the
transfer clock
Output transmission data at
the rising edge of the
transfer clock
Set-up
1
/ f
8
/ f
32
)
SSi port function
enable
Clock phase set
Serial input port set
Item
2. Serial Interface Special Function
O
O
O
SSi function disabled
SSi function enabled
Without clock delay
T
(master mode)
With clock delay
ST
(slave mode)
X
Di, R
X
Di, SR
X
Set-up
Di selected
X
Di selected