m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 53

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Figure 2.3.4. Serial I/O-related registers (3)
U A R T i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 ( i = 0 t o 3 )
b7 b6 b5 b 4 b 3 b 2 b 1 b 0
UARTi transmit/receive control register 1 (i= 0 to 3)
b7
b6
b5
b4
b3
b2
page 44 of 354
b1
Note 1: Set the corresponding port direction register to “0”.
Note 2: UART2 transfer pin (TxD
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Note 4: The corresponding port register and port direction register are invalid.
b0
UFORM T r a n s f e r f o r m a t s e l e c t b i t
N C H
( N o t e 2 )
CKPOL
T X E P T
s y m b o l
C L K 0
C L K 1
C R S
C R D
Note 1: When disabling the error signal output, set the UiERE bit to “0” after setting the
Bit Symbol
B i t
UiRRM
UiLCH
UiERE
UiIRS
U i C 0 ( i = 0 t o 3 )
TE
RE
RI
TI
It cannot be set to CMOS output.
UiMR register.
S y m b o l
( N o t e 3 )
D a t a o u t p u t s e l e c t b i t
B R G c o u n t s o u r c e
s e l e c t b i t
C T S / R T S f u n c t i o n
s e l e c t b i t
T r a n s m i t r e g i s t e r e m p t y
f l a g
C T S / R T S d i s a b l e b i t
CLK polarity select bit
Symbol
UiC1 (i=0 to 3)
Transmit enable
Transmit buffer
empty flag
Receive enable
bit
Receive
complete flag
UARTi transmit
interrupt cause
select bit
UARTi continuous
receive mode
enable bit
Data logic
select bit
Error signal
output enable bit
bit
Bit Name
B i t n a m e
03AD
Set to “0”
The value is
indeterminate when read.
0 : Transmit disabled
1 : Transmit enabled
0 : Data present in transmit buffer register
1 : No data present in transmit buffer register
0 : Receive disabled
1 : Receive enabled
0 : Data packet in receive buffer register
1 : No data packet in receive buffer register
0 : Transmit buffer empty (TI =1)
1 : Transmit buffer completed ( TXEPT =1)
0 : Continuous receive
1 : Continuous receive
0 : No reverse
1 : Reverse
(clock synchronous
0 3 A C
serial I/O mode)
mode disabled
mode enabled
16
2
, 036D
b1 b0
0 0 : f
0 1 : f
1 0 : f
1 1 : Inhibited
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 4)
0 : Data present in transmit register
1 : No data present in transmit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : TxDi/SDAi and SCLi pin is CMOS
1 : TxDi/SDAi and SCLi pin is
0 : Transmit data is output at
1 : Transmit data is output at
0 : LSB first
1 : MSB first
Function
: P7
( D u r i n g c l o c k s y n c h r o n o u s
Address
1 6
(during transmission)
register (transmission completed)
output
N-channel open drain output
falling edge of transfer clock
and receive data is input at
rising edge
rising edge of transfer clock
and receive data is input at
falling edge
, 0 3 6 C
0
16
1
8
32
s e r i a l I / O m o d e )
and SCL2: P7
, 033D
is selected
is selected
is selected
A d d r e s s
F u n c t i o n
1 6
16
, 0 3 3 C
, 032D
Set to “0”
0 : Output disabled
1 : Output enabled
1 6
16
, 0 3 2 C
(UART mode)
1
) is N-channel open drain output.
Function
(Note 1)
1 6
When reset
,
b1 b0
0 0 : f
0 0 : f
0 0 : f
0 0 : f
0 1 : f
0 1 : f
0 1 : f
0 1 : f
1 0 : f
1 0 : f
1 0 : f
1 0 : f
1 1 : Inhibited
1 1 : Inhibited
1 1 : Inhibited
1 1 : Inhibited
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 4)
0 : Data present in transmit register
1 : No data present in transmit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
Set to “0”
0 : LSB first
1 : MSB first
0 : T x D i / S D A i a n d S C L i p i n i s C M O S
1 : T x D i / S D A i a n d S C L i p i n i s
(during transmission)
register (transmission completed)
o u t p u t
N - c h a n n e l o p e n d r a i n o u t p u t
02
2. Clock-Synchronous Serial I/O
16
( D u r i n g U A R T m o d e )
1
1
1
1
8
8
8
8
32
32
32
32
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
R W
W h e n r e s e t
F u n c t i o n
0 8
1 6
R
W