m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 256

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 2.10.7. Example of operation of repeated transfer mode
M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Operation
BCLK
Address bus
RD signal
WR signal
Data bus
Write signal to
software DMAi
request bit
DMAi
request bit
DMA transfer
counter
DMAi
interrupt
request bit
DMAi
enable bit
2.10.3 Operation of DMAC (repeated transfer mode)
In repeat transfer mode, choose functions from the items shown in Table 2.10.2. Operations of the circled
items are described below. Figure 2.10.7 shows an example of operation and Figure 2.10.8 shows the
set-up procedure.
“1”
• In the case in which the number of transfer times is set to 2.
Table 2.10.2. Choosed functions
(1) When software trigger is selected, setting software DMA request bit to “1” generates a DMA
(2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAi
(3) Though DMAi transfer counter is underflowed, DMA enable bit is still “1”. The DMA interrupt
(4) After DMAi transfer counter is underflowed, when the next DMA request is generated, DMA
Transfer space
Unit of transfer
CPU use
Indeterminate
transfer request signal.
forward-direction address pointer are transferred to the address indicated by the DMAi desti-
nation pointer. When data transfer starts directly after DMAC becomes active, the value of
the DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the
value of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer.
Each time a DMA transfer request signal is generated, 2 byte of data is transferred. The
DMAi transfer counter is down counted, and the DMAi forward-direction address pointer is up
counted.
request bit changes to “1” simultaneously.
transfer is repeated from (1).
CPU use
(1) Request signal for a DMA transfer occurs
Item
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Destination
Destination
Source
(2) Data transfer begins
Source
01
O
O
16
Fixed address from an arbitrary 1 M bytes space
Arbitrary 1 M bytes space from a fixed address
8 bits
Fixed address from fixed address
16 bits
Dummy cycle
Cleared to “0” when interrupt request is accepted, or cleared by software
Dummy cycle
CPU use
00
16
CPU use
Destination
Destination
Source
Source
(3) Underflow
Set-up
Dummy cycle
Dummy cycle
CPU use
FF
16
CPU use
Destination
Destination
Source
Source
01
16
Dummy cycle
2. DMAC
Dummy cycle
00
CPU use
16
CPU use