m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 184

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
(2) Control Transfer: Endpoint 0 Receive
The endpoint 0 receives the packet data from the host CPU in the setup stage or the data stage by the
control write transfer. When the receive of a valid SETUP packet or a data packet completes, the
SETUP flag and the OUT_BUF_RDY flag are automatically set to “1”, and the number of bytes of
receive data are set in USB endpoint 0 OUT write count register (address 029C
only amount equal to received byte count from the endpoint 0 OUT FIFO. Every time that one-byte
data is read from OUT FIFO, the internal write pointer is automatically decremented by “2” in word
access and by “1” in byte access. The contents of internal write pointer cannot be read.
When the data read from OUT FIFO is completed, simultaneously set “1” to CLR_OUT_BUF_RDY bit
and SET_DATA_END bit. (When the SETUP packet is received, clearing the SETUP flag by setting
“1” to CLR_SETUP bit is required.) Therefore, the OUT_BUF_RDY flag is cleared and the
DATA_END flag is set to “1”.
The USB function unit proceeds to the status phase process when the DATA_END flag is set to “1”.
When the status phase completes, the DATA_END flag is cleared to “0”.
Manage the stage of control transfer by software.
When the SETUP packet is received, the USB endpoint 0 interrupt occurs regardless of setting of
continuous transfer mode enable bit (The OUT_BUF_RDY flag and the SETUP flag are set to “1”).
1: Check that one packet data is received in OUT FIFO.
2: Read the number of bytes of receive packet data from USB endpoint 0 OUT write count register.
3: Read the data of only amount equal to determined in the above-mentioned 2: from OUT FIFO. To
4: With CLR_OUT_BUF_RDY bit being set to “1”, the OUT_BUF_RDY flag is cleared to complete
Determine the amount of data to read from OUT FIFO.
Example of one packet data receive procedure
analyze the received data, the subsequent stage and operation are determined based on the read
data.
fetch of the receive one packet, and manage the next stage control. At this time, when the SETUP
packet is received, the SETUP flag is also cleared by setting “1” to CLR_SETUP bit.
• For shifting into the status stage even if the next data to be received or transmitted does not
• For responding with STALL response to the next token, simultaneously set
• When the valid new SETUP packet is received after setting SEND_STALL bit, clear
exist, simultaneously set CLR_OUT_BUF_RDYbit (and also CLR_SETUP bit for the SETUP
packet) and SET_DATA_END bit to “1”.
CLR_OUT_BUF_RDY bit (and also CLR_SETUP bit for the SETUP packet) and SEND_STALL
bit to “1”.
SEND_STALL bit and set CLR_OUT_BUF_RDY bit to “1” (and also CLR_SETUP bit for the
SETUP packet).
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). Read the data of
2. USB function