c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 102

• Manufacturer Part Number: c8051t602
• Description: Mixed Signal Otp Eprom Mcu Family
• Manufacturer: Silicon Laboratories

C8051T600/1/2/3/4/5
13.3. General Purpose Port I/O
Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for
general purpose I/O. Port0 is accessed through a corresponding special function register (SFR) that is
both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is latched
to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins are
returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the
Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the
execution of the read-modify-write instructions. The read-modify-write instructions when operating on a
Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SET, when the
destination is an individual bit in a Port SFR. For these instructions, the value of the register (not the pin) is
read, modified, and written back to the SFR.
102
Bit7:
Bit6:
Bits5–3: UNUSED: Read=000b. Write = don’t care.
Bit2:
Bit1:
Bit0:
WEAKPUD XBARE
R/W
Bit7
WEAKPUD: Port I/O Weak Pull-up Disable.
0: Weak Pull-ups enabled (except for Ports whose I/O are configured as push-pull).
1: Weak Pull-ups disabled.
XBARE: Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
T1E: T1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
T0E: T0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
ECIE: PCA0 Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
SFR Definition 13.3. XBR2: Port I/O Crossbar Register 2
R/W
Bit6
R/W
Bit5
-
R/W
Bit4
-
Rev. 0.5
R/W
Bit3
-
T1E
R/W
Bit2
T0E
R/W
Bit1
ECIE
R/W
Bit0
SFR Address:
00000000
Reset Value
0xE3