c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 19

• Manufacturer Part Number: c8051t602
• Description: Mixed Signal Otp Eprom Mcu Family
• Manufacturer: Silicon Laboratories

1.4.
C8051T600/1/2/3/4/5 devices include a byte-wide I/O Port that behaves like a typical 8051 Port with a few
enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as
digital I/Os may additionally be configured for push-pull or open-drain output. The “weak pullups” that are
fixed on typical 8051 devices may be globally disabled, providing additional power savings.
Perhaps the most unique Port I/O enhancement is the Digital Crossbar. This is a digital switching network
that allows mapping of internal digital system resources to Port I/O pins (See Figure 1.5). On-chip counter/
timers, serial buses, HW interrupts, comparator output, and other digital signals in the controller can be
configured to appear on the Port I/O pins using the Crossbar Control registers. This allows the user to
select the exact mix of general purpose Port I/O and digital resources needed for the application.
1.5.
The C8051T600/1/2/3/4/5 Family includes an SMBus/I
baud rate configuration. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention. Both serial buses can be used at
the same time.
1.6.
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the three 16-bit general
purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three pro-
grammable capture/compare modules. The PCA clock is derived from one of six sources: the system clock
divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system
clock, or the external oscillator clock source divided by 8. The external clock source selection is useful for
Highest
Priority
Lowest
Priority
Programmable Digital I/O and Crossbar
Serial Ports
Programmable Counter Array
SYSCLK
Outputs
SMBus
T0, T1
UART
PCA
CP0
Port Latch
2
2
2
4
2
Figure 1.5. Digital Crossbar Diagram
P0
(P0.0-P0.7)
8
Rev. 0.5
XBR2 Registers
XBR0, XBR1,
Crossbar
Decoder
2
Priority
Digital
C interface and a full-duplex UART with enhanced
C8051T600/1/2/3/4/5
8
P0MDIN Registers
P0MDOUT,
Cells
P0
I/O
P0.0
P0.7
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