c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 132

• Manufacturer Part Number: c8051t602
• Description: Mixed Signal Otp Eprom Mcu Family
• Manufacturer: Silicon Laboratories

C8051T600/1/2/3/4/5
Crossbar Decoder” on page 98
C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is clocked by the sys-
tem clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock Scale bits in
CKCON (see SFR Definition 16.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 9.11). Setting GATE0 to ‘1’
allows the timer to be controlled by the external input signal /INT0 (see
Descriptions” on page 73
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 9.11).
132
/INT0
T0
Crossbar
Pre-scaled Clock
SYSCLK
IN0PL
GATE0
TR0
0
1
1
1
X = Don't Care
), facilitating pulse width measurements.
XOR
Figure 16.1. T0 Mode 0 Block Diagram
for information on selecting and configuring external I/O pins.) Clearing
TR0
0
1
GATE0
M
H
T
2
X
0
1
1
CKCON
M
T
2
L
M
T
1
0
1
M
T
0
C
S
A
1
Rev. 0.5
S
C
A
0
G
A
T
E
1
/INT0
C
T
1
/
M
T
1
1
TMOD
X
X
0
1
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 bits)
TL0
N
P
1
L
I
Counter/Timer
N
1
S
L
2
I
Section “9.3.5. Interrupt Register
IT01CF
N
1
S
L
1
I
Disabled
Disabled
Enabled
Enabled
N
S
1
L
0
I
N
P
0
L
I
(8 bits)
TH0
N
0
S
L
2
I
N
0
S
L
1
I
N
S
0
L
0
I
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt