c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 111

• Manufacturer Part Number: c8051t602
• Description: Mixed Signal Otp Eprom Mcu Family
• Manufacturer: Silicon Laboratories

Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 14.2 shows the min-
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
With the SMBTOE bit set, Timer 2 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see
to reload while SCL is high, and allow Timer 2 to count when SCL is low. The Timer 2 interrupt service rou-
tine should be used to reset SMBus communication by disabling and re-enabling the SMBus. Timer 2 con-
figuration is described in
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 14.4). When a Free Timeout is detected, the interface will respond as if a STOP was detected (an
interrupt will be generated, and STO will be set).
Timer Source
Overflows
SCL
*Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. The s/w
EXTHOLD
Section “14.3.3. SCL Low Timeout” on page 108
delay occurs between the time SMB0DAT or ACK is written and when SI is cleared.
Note that if SI is cleared in the same write that defines the outgoing ACK value, s/w
delay is zero.
0
1
Table 14.2. Minimum SDA Setup and Hold Times
T
Low
Figure 14.4. Typical SMBus SCL Generation
Section “16.2. Timer 2” on page 139
Minimum SDA Setup Time
1 system clock + s/w delay*
T
low
11 system clocks
- 4 system clocks
T
High
OR
Rev. 0.5
C8051T600/1/2/3/4/5
.
Minimum SDA Hold Time
). The SMBus interface will force Timer 2
12 system clocks
3 system clocks
SCL High Timeout
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