c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 81

• Manufacturer Part Number: c8051t602
• Description: Mixed Signal Otp Eprom Mcu Family
• Manufacturer: Silicon Laboratories

10. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled dur-
ing and after the reset. For V
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Refer to
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source (
Once the system clock source is stable, program execution begins at location 0x0000.
EXTCLK
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
Section “17.3. Watchdog Timer Mode” on page 151
P0.x
P0.y
Oscillator
External
Source
Internal
Clock
Section “12. Oscillators” on page 91
Comparator 0
DD
+
-
Clock Select
System
Clock
Monitor and power-on resets, the RST pin is driven low until the device
Figure 10.1. Reset Sources
C0RSEF
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
CIP-51
Core
Handler
Rev. 0.5
WDT
PCA
EN
System Reset
Power On
Monitor
Supply
Reset
for information on selecting and configuring
C8051T600/1/2/3/4/5
(Software Reset)
SWRSF
details the use of the Watchdog Timer).
'0'
Illegal OTP
operation
(wired-OR)
Reset
Funnel
/RST
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