c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 153

• Manufacturer Part Number: c8051t602
• Description: Mixed Signal Otp Eprom Mcu Family
• Manufacturer: Silicon Laboratories

17.3.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
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•
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The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The Watchdog
Timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 17.4, this results in a WDT
timeout interval of 3072 system clock cycles. Table 17.3 lists some example timeout intervals for typical
system clocks, assuming SYSCLK / 12 as the PCA clock source.
Notes:
Disable the WDT by writing a ‘0’ to the WDTE bit.
Select the desired PCA clock source (with the CPS2–CPS0 bits).
Load PCA0CPL2 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
Enable the WDT by setting the WDTE bit to ‘1’.
Reload the WDT by writing any value to PCA0CPH2.
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value of 0x00 at the update time.
2. Internal reset frequency for SYSCLK (Internal Oscillator/8).
System Clock (Hz)
24,500,000
24,500,000
24,500,000
12,250,000
12,250,000
12,250,000
3,062,500
3,062,500
3,062,500
6,125,000
6,125,000
6,125,000
Table 17.3. Watchdog Timer Timeout Intervals
2
2
2
Rev. 0.5
PCA0CPL2
255
128
255
128
255
128
255
128
32
32
32
32
C8051T600/1/2/3/4/5
Timeout Interval (ms)
1
128.4
129.5
32.1
16.2
64.2
32.4
64.7
16.6
33.1
257
4.1
8.3
153