c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 72

• Manufacturer Part Number: c8051t602
• Description: Mixed Signal Otp Eprom Mcu Family
• Manufacturer: Silicon Laboratories

C8051T600/1/2/3/4/5
9.3.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
72
Interrupt Source
Reset
External Interrupt 0 (/INT0)
Timer 0 Overflow
External Interrupt 1 (/INT1)
Timer 1 Overflow
UART0
Timer 2 Overflow
SMBus Interface
ADC0 Window Compare
ADC0 Conversion
Complete
Programmable Counter
Array
Comparator0 Falling Edge
Comparator0 Rising Edge
Interrupt
0x000B
0x001B
0x002B
0x003B
0x004B
0x005B
0x0000
0x0003
0x0013
0x0023
0x0033
0x0043
0x0053
Vector
Table 9.4. Interrupt Summary
Priority
Order
Top
10
11
0
1
2
3
4
5
6
7
8
9
Rev. 0.5
Pending Flag
None
IE0 (TCON.1)
TF0 (TCON.5)
IE1 (TCON.3)
TF1 (TCON.7)
RI0 (SCON0.0)
TI0 (SCON0.1)
TF2H
(TMR2CN.7)
TF2L
(TMR2CN.6)
SI (SMB0CN.0)
AD0WINT
(ADC0CN.3)
AD0INT
(ADC0CN.5)
CF (PCA0CN.7)
CCFn
(PCA0CN.n)
CP0FIF
(CPT0CN.4)
CP0RIF
(CPT0CN.5)
N/A N/A
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Enable
Flag
Always
Enabled
EX0 (IE.0) PX0 (IP.0)
ET0 (IE.1) PT0 (IP.1)
EX1 (IE.2) PX1 (IP.2)
ET1 (IE.3) PT1 (IP.3)
ES0 (IE.4) PS0 (IP.4)
ET2 (IE.5) PT2 (IP.5)
ESMB0
(EIE1.0)
EWADC0
(EIE1.1)
EADC0C
(EIE1.2)
EPCA0
(EIE1.3)
ECP0F
(EIE1.4)
ECP0R
(EIE1.5)
Priority
Control
Always
Highest
PSMB0
(EIP1.0)
PWADC0
(EIP1.1)
PADC0C
(EIP1.2)
PPCA0
(EIP1.3)
PCP0F
(EIP1.4)
PCP0R
(EIP1.5)