c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 83

• Manufacturer Part Number: c8051t602
• Description: Mixed Signal Otp Eprom Mcu Family
• Manufacturer: Silicon Laboratories

10.2. Power-Fail Reset/V
If the power supply monitor is enabled, when a power-down transition or power irregularity causes V
drop below V
(see Figure 10.2). When V
state. Note that even though internal data memory contents are not altered by the power-fail reset, it is
impossible to determine if V
‘1’, the data may no longer be valid. The V
defined state (enabled/disabled) is not altered by any other reset source. For example, if the V
is enabled and a software reset is performed, the V
monitor is enabled by writing a ‘1’ to the PORSF bit in register RSTSRC. See Figure 10.2 for V
timing; note that the reset delay is not incurred after a V
acteristics of the V
Important Note: Enabling the V
tem reset. The device will then return from the reset state with the V
‘1’ to the PORSF flag when the V
10.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 10.2 for complete RST pin
specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
10.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,
this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables
it. The state of the RST pin is unaffected by a missing clock detector reset.
10.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0–), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying
Comparator0 as the reset source; otherwise, this bit reads ‘0’. The state of the RST pin is unaffected by a
Comparator0 reset.
10.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in
page 151
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to ‘1’. The state of the RST pin is unaffected by a WDT reset.
; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
RST
, the power supply monitor will drive the RST pin low and hold the CIP-51 in a reset state
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monitor.
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returns to a level above V
dropped below the level required for data retention. If the PORSF flag reads
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monitor when it is not already enabled will immediately generate a sys-
Monitor
monitor is already enabled does not cause a system reset.
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Rev. 0.5
monitor is disabled after power-on resets; however its
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monitor will still be enabled after the reset. The V
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RST
monitor reset. See Table 10.2 for electrical char-
Section “17.3. Watchdog Timer Mode” on
, the CIP-51 will be released from the reset
C8051T600/1/2/3/4/5
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monitor enabled. Writing a logic
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monitor
monitor
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