c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 103

• Manufacturer Part Number: c8051t602
• Description: Mixed Signal Otp Eprom Mcu Family
• Manufacturer: Silicon Laboratories

Bits7–0: P0.[7:0]
Bits7–0: Input Configuration Bits for P0.7–P0.0 (respectively)
Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis-
P0.7
R/W
R/W
R/W
Bit7
Bit7
Bit7
Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers
0: Logic Low Output.
1: Logic High Output (open-drain if corresponding P0MDOUT.n bit = 0)
Read - Always reads ‘1’ if selected as analog input in register P0MDIN. Directly reads Port
pin when configured as digital input.
0: P0.n pin is logic low.
1: P0.n pin is logic high.
Port pins configured as analog inputs have their weak pull-up, digital driver, and digital
receiver disabled.
0: Corresponding P0.n pin is configured as an analog input.
1: Corresponding P0.n pin is configured as a digital input.
ter P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
(Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless
of the value of P0MDOUT).
P0.6
R/W
R/W
R/W
Bit6
Bit6
Bit6
SFR Definition 13.6. P0MDOUT: Port0 Output Mode
SFR Definition 13.5. P0MDIN: Port0 Input Mode
P0.5
R/W
R/W
R/W
Bit5
Bit5
Bit5
SFR Definition 13.4. P0: Port0
P0.4
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 0.5
P0.3
R/W
R/W
R/W
Bit3
Bit3
Bit3
P0.2
R/W
R/W
R/W
Bit2
Bit2
Bit2
C8051T600/1/2/3/4/5
P0.1
R/W
R/W
R/W
Bit1
Bit1
Bit1
(bit addressable)
P0.0
R/W
R/W
R/W
Bit0
Bit0
Bit0
SFR Address:
SFR Address:
SFR Address:
00000000
Reset Value
Reset Value
Reset Value
11111111
11111111
0xF1
0xA4
0x80
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