c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 8

• Manufacturer Part Number: c8051t602
• Description: Mixed Signal Otp Eprom Mcu Family
• Manufacturer: Silicon Laboratories

C8051T600/1/2/3/4/5
14. SMBus
15. UART0
16. Timers
17. Programmable Counter Array
18. Revision Specific Behavior
19. C2 Interface
8
Figure 13.2. Port I/O Cell Block Diagram ................................................................. 97
Figure 13.3. Crossbar Priority Decoder with XBR0 = 0x00 ...................................... 98
Figure 13.4. Crossbar Priority Decoder with XBR0 = 0x44 ...................................... 99
Figure 14.1. SMBus Block Diagram ....................................................................... 105
Figure 14.2. Typical SMBus Configuration ............................................................. 106
Figure 14.3. SMBus Transaction ............................................................................ 107
Figure 14.4. Typical SMBus SCL Generation......................................................... 111
Figure 14.5. Typical Master Transmitter Sequence................................................ 117
Figure 14.6. Typical Master Receiver Sequence.................................................... 118
Figure 14.7. Typical Slave Receiver Sequence...................................................... 119
Figure 14.8. Typical Slave Transmitter Sequence.................................................. 120
Figure 15.1. UART0 Block Diagram ....................................................................... 123
Figure 15.2. UART0 Baud Rate Logic .................................................................... 124
Figure 15.3. UART Interconnect Diagram .............................................................. 125
Figure 15.4. 8-Bit UART Timing Diagram............................................................... 125
Figure 15.5. 9-Bit UART Timing Diagram............................................................... 126
Figure 15.6. UART Multi-Processor Mode Interconnect Diagram .......................... 127
Figure 16.1. T0 Mode 0 Block Diagram.................................................................. 132
Figure 16.2. T0 Mode 2 Block Diagram.................................................................. 133
Figure 16.3. T0 Mode 3 Block Diagram.................................................................. 134
Figure 16.4. Timer 2 16-Bit Mode Block Diagram .................................................. 139
Figure 16.5. Timer 2 8-Bit Mode Block Diagram .................................................... 140
Figure 17.1. PCA Block Diagram............................................................................ 143
Figure 17.2. PCA Counter/Timer Block Diagram.................................................... 144
Figure 17.3. PCA Interrupt Block Diagram ............................................................. 145
Figure 17.4. PCA Capture Mode Diagram.............................................................. 146
Figure 17.5. PCA Software Timer Mode Diagram .................................................. 147
Figure 17.6. PCA High Speed Output Mode Diagram............................................ 148
Figure 17.7. PCA Frequency Output Mode ............................................................ 149
Figure 17.8. PCA 8-Bit PWM Mode Diagram ......................................................... 150
Figure 17.9. PCA 16-Bit PWM Mode...................................................................... 151
Figure 17.10. PCA Module 2 with Watchdog Timer Enabled ................................. 152
Figure 18.1. Device Package - SOIC 14 ................................................................ 159
Figure 18.2. Device Package - QFN 10.................................................................. 159
Figure 19.1. Typical C2 Pin Sharing....................................................................... 166
Rev. 0.5