c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 40

• Manufacturer Part Number: c8051t602
• Description: Mixed Signal Otp Eprom Mcu Family
• Manufacturer: Silicon Laboratories

C8051T600/1/2/3/4/5
40
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
Bit2:
Bits1–0: AMP0GN1–0: ADC Gain Control Bits.
Bits7–0: ADC0 Data Word bits 9–2.
Bits7–6: ADC0 Data Word bits 1–0.
Bits5–0: Read: 000000b, Write = Don’t Care
AD0SC4
R/W
R/W
R/W
Bit7
D9
Bit7
D1
Bit7
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock require-
ments are given in Table 5.1.
Note : if the OTP Power Controller is enabled (OTPPCE = '1'), AD0SC must be set to at
least "00001" for proper ADC operation.
AD08BE: 8-Bit Mode Enable.
0: ADC operates in 10-bit mode (normal).
1: ADC operates in 8-bit mode.
00: Gain = 0.5
01: Gain = 1
ADC0H holds the upper 8 bits of output data from the most recently completed ADC0 con-
version. In 8-bit compatibility mode, the ADC0H register holds all 8 bits of the conversion
data word.
ADC0L holds the lowest 2 bits of output data from the most recently completed ADC0 con-
version. In 8-bit compatibility mode, the ADC0L register always returns 0x00.
AD0SC
AD0SC3
R/W
R/W
R/W
Bit6
Bit6
Bit6
SFR Definition 5.5. ADC0H: ADC0 Data Word High Byte
D8
D0
SFR Definition 5.6. ADC0L: ADC0 Data Word Low Byte
SFR Definition 5.4. ADC0CF: ADC0 Configuration
=
SYSCLK
--------------------- - 1
CLK
AD0SC2
R/W
R/W
Bit5
Bit5
Bit5
D7
R
-
SAR
–
AD0SC1
R/W
R/W
Bit4
Bit4
Bit4
D6
R
-
AD0SC0
Rev. 0.5
R/W
R/W
Bit3
Bit3
Bit3
D5
R
-
AD08BE AMP0GN1 AMP0GN0 11111000
R/W
R/W
Bit2
Bit2
Bit2
D4
R
-
R/W
R/W
Bit1
D3
Bit1
Bit1
R
-
R/W
R/W
Bit0
Bit0
Bit0
D2
R
-
SFR Address:
SFR Address:
SFR Address:
00000000
00000000
Reset Value
Reset Value
Reset Value
0xBD
0xBC
0xBE