mc9s08qd4 Freescale Semiconductor, Inc, mc9s08qd4 Datasheet - Page 130

• Manufacturer Part Number: mc9s08qd4
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Internal Clock Source (S08ICSV1)
9.4
9.4.1
The seven states of the ICS are shown as a state diagram and are described below. The arrows indicate the
allowed movements between the states.
9.4.1.1
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
conditions occur:
In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL loop will lock the frequency to 512 times the filter frequency, as
selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the internal reference
clock is enabled.
130
FLL Bypassed
External Low
Power(FBELP)
•
•
•
IREFS=0
CLKS=10
BDM Disabled
and LP=1
CLKS bits are written to 00
IREFS bit is written to 1
RDIV bits are written to divide trimmed reference clock to be within the range of 31.25 kHz to
39.0625 kHz.
Functional Description
Operational Modes
FLL Engaged Internal (FEI)
Entered from any state
when MCU enters stop
IREFS=0
CLKS=10
BDM Enabled
or LP =0
FLL Bypassed
External (FBE)
MC9S08QD4 Series MCU Data Sheet, Rev. 3
Figure 9-7. Clock Switching Modes
FLL Engaged
External (FEE)
FLL Engaged
Internal (FEI)
IREFS=1
CLKS=00
IREFS=0
CLKS=00
Stop
FLL Bypassed
Internal (FBI)
Returns to state that was active
before MCU entered stop, unless
reset occurs while in stop.
IREFS=1
CLKS=01
BDM Enabled
or LP=0
Freescale Semiconductor
FLL Bypassed
Internal Low
Power(FBILP)
IREFS=1
CLKS=01
BDM Disabled
and LP=1