mc9s08qd4 Freescale Semiconductor, Inc, mc9s08qd4 Datasheet - Page 70

• Manufacturer Part Number: mc9s08qd4
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 6 Parallel Input/Output Control
The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is
enabled, and also controls the source for port data register reads. The input buffer for the associated pin is
always enabled unless the pin is enabled as an analog function or is an output-only pin.
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.
However, the data direction register bit will continue to control the source for reads of the port data register.
When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value
of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled. In
general, whenever a pin is shared with both an alternate digital function and an analog function, the analog
function has priority such that if both the digital and analog functions are enabled, the analog function
controls the pin.
It is a good programming practice to write to the port data register before changing the direction of a port
pin to become an output. This ensures that the pin will not be driven momentarily with an old data value
that happened to be in the port data register.
6.2
Associated with the parallel I/O ports is a set of registers located in the high-page register space that
operate independently of the parallel I/O registers. These registers are used to control pullups, slew rate
and drive strength for the pins.
6.3
Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An
explanation of pin behavior for the various stop modes follows:
70
Pin Control — Pullup, Slew Rate and Drive Strength
Pin Behavior in Stop Modes
Port Read
BUSCLK
Data
MC9S08QD4 Series MCU Data Sheet, Rev. 3
Figure 6-1. Parallel I/O Block Diagram
PTxDDn
D
D
PTxDn
Q
Q
1
0
Synchronizer
Output Enable
Output Data
Freescale Semiconductor
Input Data