mc9s08qd4 Freescale Semiconductor, Inc, mc9s08qd4 Datasheet - Page 47

• Manufacturer Part Number: mc9s08qd4
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Table 4-7
Freescale Semiconductor
Reset
PRDIV8
DIVLD
Field
DIV
5:0
7
6
W
R
shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.
DIVLD
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for flash.
1 FCDIV has been written since reset; erase and program operations enabled for flash.
Prescale (Divide) Flash Clock by 8
0 Clock input to the flash clock divider is the bus rate clock.
1 Clock input to the flash clock divider is the bus rate clock divided by 8.
Divisor for Flash Clock Divider — The flash clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV field plus one. The resulting frequency of the internal
flash clock must fall within the range of 200 kHz to 150 kHz for proper flash operations. Program/Erase timing
pulses are one cycle of this internal flash clock which corresponds to a range of 5 μs to 6.7 μs. The automated
programming logic uses an integer number of these pulses to complete an erase or program operation. See
Equation 4-1
0
7
200 kHz
150 kHz
8 MHz
4 MHz
2 MHz
1 MHz
f
Bus
= Unimplemented or Reserved
PRDIV8
and
(Binary)
PRDIV8
0
6
Equation
if PRDIV8 = 1 – f
0
0
0
0
0
0
Figure 4-5. Flash Clock Divider Register (FCDIV)
if PRDIV8 = 0 – f
Table 4-6. FCDIV Register Field Descriptions
MC9S08QD4 Series MCU Data Sheet, Rev. 3
Table 4-7. Flash Clock Divider Settings
4-2.
(Decimal)
0
5
DIV
39
19
9
4
0
0
FCLK
FCLK
= f
0
4
= f
Bus
200 kHz
200 kHz
200 kHz
200 kHz
200 kHz
150 kHz
f
FCLK
Bus
Description
÷ (8 × (DIV + 1))
÷ (DIV + 1)
3
0
Program/Erase Timing Pulse
(5 μs Min, 6.7 μs Max)
DIV
Chapter 4 Memory Map and Register Definition
6.7 μs
0
5 μs
5 μs
5 μs
5 μs
5 μs
2
0
1
Eqn. 4-1
Eqn. 4-2
0
0
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