mc9s08qd4 Freescale Semiconductor, Inc, mc9s08qd4 Datasheet - Page 92

• Manufacturer Part Number: mc9s08qd4
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 7 Central Processor Unit (S08CPUV2)
92
Source
Form
TXS
WAIT
Source Form: Everything in the source forms columns, except expressions in italic characters, is literal information which must appear in
Operation Symbols:
CCR Bits:
the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic and the characters (# , ( ) and +) are always a literal
characters.
n
opr8i
opr16i
opr8a
opr16a
oprx8
oprx16
rel
A
CCR
H
M
n
opr
PC
PCH
PCL
rel
SP
SPL
X
&
|
⊕
( )
+
–
×
÷
#
←
:
V
H
I
N
Z
C
Accumulator
Condition code register
Index register high byte
Memory location
Any bit
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative program counter offset byte
Stack pointer
Stack pointer low byte
Index register low byte
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Add
Subtract, Negation (two’s complement)
Multiply
Divide
Immediate value
Loaded with
Concatenated with
Overflow bit
Half-carry bit
Interrupt mask
Negative bit
Zero bit
Carry/borrow bit
Any label or expression that evaluates to a single integer in the range 0-7.
Any label or expression that evaluates to an 8-bit immediate value.
Any label or expression that evaluates to a 16-bit immediate value.
Any label or expression that evaluates to an 8-bit direct-page address ($00xx).
Any label or expression that evaluates to a 16-bit address.
Any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing.
Any label or expression that evaluates to a 16-bit value, used for indexed addressing.
Any label or expression that refers to an address that is within –128 to +127 locations from the start of the next instruction.
Operation
Transfer Index Reg. to SP
SP ← (H:X) – $0001
Enable Interrupts; Wait for Interrupt
I bit ← 0; Halt CPU
Table 7-2. Instruction Set Summary (Sheet 9 of 9)
MC9S08QD4 Series MCU Data Sheet, Rev. 3
INH
INH
Addressing Modes:
Cycle-by-Cycle Codes:
CCR Effects:
DIR
EXT
IMM
INH
IX
IX1
IX2
IX+
IX1+
REL
SP1
SP2
f
p
r
s
u
v
w
–
U
Direct addressing mode
Extended addressing mode
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Indexed, no offset, post increment addressing mode
Indexed, 8-bit offset, post increment addressing mode
Relative addressing mode
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Free cycle. This indicates a cycle where the CPU
does not require use of the system buses. An f
cycle is always one cycle of the system bus clock
and is always a read cycle.
Progryam fetch; read from next consecutive
location in program memory
Read 8-bit operand
Push (write) one byte onto stack
Pop (read) one byte from stack
Read vector from $FFxx (high byte first)
Write 8-bit operand
Set or cleared
Not affected
Undefined
Object Code
94
8F
2+
2
Cyc-by-Cyc
Details
fp
fp...
Freescale Semiconductor
VH I N Z C
– – – – – –
– – 0 – – –
on CCR
Affect