mc9s08qd4 Freescale Semiconductor, Inc, mc9s08qd4 Datasheet - Page 59

• Manufacturer Part Number: mc9s08qd4
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

5.6.1
When power is initially applied to the MCU, or when the supply voltage drops below the V
POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the MCU
in reset until the supply has risen above the V
following a POR.
5.6.2
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply
voltage has risen above the level determined by LVDV. The LVD bit in the SRS register is set following
either an LVD reset or POR.
5.6.3
When a low voltage condition is detected and the LVD circuit is configured using SPMSC1 for interrupt
operation (LVDE set, LVDIE set, and LVDRE clear), then LVDF in SPMSC1 will be set and an LVD
interrupt request will occur.
5.6.4
The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is
approaching, but is above, the LVD voltage. The LVW does not have an interrupt associated with it. There
are two user selectable trip voltages for the LVW, one high (V
voltage is selected by LVWV in SPMSC3.
5.7
The real-time interrupt function can be used to generate periodic interrupts. The RTI can accept two
sources of clocks, the 1 kHz internal clock or an 32 kHz ICS clock if available. The RTICLKS bit in
SRTISC is used to select the RTI clock source.
Both clock source can be used when the MCU is in run, wait or stop3 mode. When using the 32 kHz ICS
clock in stop3, it must be enabled in stop (EREFSTEN = 1) and configured for low frequency operation
(RANGE = 0). Only the internal 1 kHz clock source can be selected to wake the MCU from stop1 or stop2
modes.
The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control
value (RTIS) used to select one of seven wakeup periods. The RTI has a local interrupt enable, RTIE, to
allow masking of the real-time interrupt. The RTI can be disabled by writing each bit of RTIS to zeroes,
and no interrupts will be generated. See
Register
Freescale Semiconductor
(SRTISC),” for detailed information about this register.
Real-Time Interrupt (RTI)
Power-On Reset Operation
LVD Reset Operation
LVD Interrupt Operation
Low-Voltage Warning (LVW)
MC9S08QD4 Series MCU Data Sheet, Rev. 3
Section 5.8.7, “System Real-Time Interrupt Status and Control
LVDL
level. Both the POR bit and the LVD bit in SRS are set
Chapter 5 Resets, Interrupts, and General System Control
LVWH
) and one low (V
LVWL
). The trip
POR
level, the
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