mc9s08qd4 Freescale Semiconductor, Inc, mc9s08qd4 Datasheet - Page 134

• Manufacturer Part Number: mc9s08qd4
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Internal Clock Source (S08ICSV1)
9.4.7
The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source for
peripheral modules. The ICS provides an output signal (ICSFFE) which indicates when the ICS is
providing ICSOUT frequencies four times or greater than the divided FLL reference clock (ICSFFCLK).
In FLL engaged mode (FEI and FEE) this is always true and ICSFFE is always high. In ICS bypass modes,
ICSFFE will get asserted for the following combinations of BDIV and RDIV values:
9.5
This section describes how to initialize and configure the ICS module. The following sections contain two
initialization examples.
9.5.1
The ICS comes out of POR configured for FEI mode with the BDIV set for divide-by 2. The internal
reference will stabilize in t
reference is stable, the FLL will acquire lock in t
Upon POR, the internal reference will require trimming to guarantee an accurate clock. Freescale
recommends using FLASH location 0xFFAE for storing the fine trim bit, FTRIM in the ICSSC register,
and 0xFFAF for storing the 8-bit trim value for the ICSTRM register. The MCU will not automatically
copy the values in these FLASH locations to the respective registers. Therefore, user code must copy these
values from FLASH to the registers.
9.5.1.1
To change from FEI or FBI clock modes to FEE or FBE clock modes, follow this procedure:
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1. Enable the external clock source by setting the appropriate bits in ICSC2.
2. If necessary, wait for the external clock source to stabilize. Typical crystal startup times are given
3. Write to ICSC1 to select the clock mode.
BDIV=00 (divide by 1), RDIV ≥ 010
BDIV=01 (divide by 2), RDIV ≥ 011
BDIV=10 (divide by 4), RDIV ≥ 100
BDIV=11 (divide by 8), RDIV ≥ 101
— If FBE will be the selected mode, also set the LP bit at this time to minimize power
in Electrical Characteristics appendix. If EREFS is set in step 1, then the OSCINIT bit will set as
soon as the oscillator has completed the initialization cycles.
Module Initialization
consumption.
Fixed Frequency Clock
ICS Module Initialization Sequence
Initialization Sequence, Internal Clock Mode to External Clock Mode
The BDIV value must not be changed to divide-by 1 without first trimming
the internal reference. Failure to do so could result in the MCU running out
of specification.
IRST
microseconds before the FLL can acquire lock. As soon as the internal
MC9S08QD4 Series MCU Data Sheet, Rev. 3
Acquire
NOTE
milliseconds.
Freescale Semiconductor