msm7630 Oki Semiconductor, msm7630 Datasheet
msm7630
Available stocks
Related parts for msm7630
msm7630 Summary of contents
Page 1
... Semiconductor ¡ Semiconductor MSM7630 Universal Speech Processor GENERAL DESCRIPTION The MSM7630 is a speech processor LSI device with internal D/A converter optimized for speech output applications such as text-to-speech conversion. FEATURES • Parallel and serial interfaces • Single 3.3V power supply • 5V interface available • ...
Page 2
... BLOCK DIAGRAM CLK PLL MCLKA TSTM TST EXINT DAC DAO1 SG TMR RST TMR STBY TMR SCLK TXD RXD DSR SIO DTR CTS RTS MPY CPU DRAMC PIO MSM7630 A23-0 D31-16 WR0,1 RD ROM SRAM RAS CAS0,1 WE PD7-0 PSTB PACK PCS PIOA POBF PIBF 2/95 ...
Page 3
... D28 D27 16 GND 17 D26 18 D25 19 D24 20 21 D23 D22 22 D21 D20 25 26 D19 D18 27 D17 28 D16 29 PD7 30 100-Pin Plastic QFP MSM7630 80 A18 79 GND 78 A17 77 A16 76 A15 75 A14 74 A13 73 A12 A11 A10 ...
Page 4
... CLK I Clock input signal Clock signal. Inverse of CLK. CLKA O Internal clock signal. RST I Reset input. STBY Standby signal. STBY suspends operation and places the MSM7630 in a standby state. I EXTINT I External interrupt signal. TSTM2,1 I Test mode select input signal. Description MSM7630 4/95 ...
Page 5
... 3 — MHz OPE — I — load V — DAE — MSM7630 Rating Unit –0.3 to +4.5 V –0.3 to +5.5 V –55 to +125 °C Range Unit 3.0 to 3.6 V –40 to +85 ° 3 –40 to +85°C) DD Typ. Max. Unit — — ...
Page 6
... A — t S_D — t H_D — t — D — t — RD Falling t — WR Rising — — t — UPORT — S_EXINT MSM7630 (V = 3 –40 to +85°C) DD OPE Typ. Max. Unit — — — — — ns — — — — ...
Page 7
... Access — t ROM — t SRAM ROM t W_ROM 3t to 12t Access SRAM W_SRAM 3t to 12t Access SRAM t W_WRD 3t Access SRAM 4t to 12t Access MSM7630 (V = 3 –40 to +85°C) DD OPE Typ. Max. Unit 2 — CYC — 10.5 t CYC — 1 — ...
Page 8
... W_ACAS — 1.5 — 1.5 — — t W_WE — t W_AWE — W_PREC — Hyper Mode t W_EDO Condition Min. — MSM7630 (V = 3 –40 to +85°C) DD OPE Typ. Max. Unit — — — Note 1 t CYC — 1 — t CYC — — ...
Page 9
... Access t W_WR (X bit = 14t Access (X bit = Access t W_AWR (X bit = 14t Access (X bit = Access t W_DWR (X bit = 14t Access (X bit = 1) MSM7630 (V = 3 –40 to +85°C) DD OPE Typ. Max. Unit — CYC 6 — CYC — ...
Page 10
... Access t W_WR (X bit = 14t Access (X bit = Access t W_AWR (X bit = 14t Access (X bit = Access W_DWR (X bit = 14t Access (X bit = 1) MSM7630 (V = 3 –40 to +85°C) DD OPE Typ. Max. Unit 2 — CYC 6 — ...
Page 11
... H_PCS — t S_PIOA — t H_PIOA — W_PACK — W_PSTB — t –t S_PD — t H_PD MSM7630 (V = 3 –40 to +85°C) DD OPE Typ. Max. Unit — — — — — — — — 0 — — — ...
Page 12
... Semiconductor TIMING DIAGRAM Clock And Reset t OSC CLK t XO CLKA RST t t W_CLKL W_CLKH XO t CLKA t W_RST MSM7630 t CYC 12/95 ...
Page 13
... A t S_D t W_ARD t W_ROM t ROM W_RD / Access t W_ROM W_RD / / /10t /12t Access MSM7630 H_D t ROM S_D H_D t ROM t RD 13/95 ...
Page 14
... A t S_D t W_ARD t W_SRAM t SRAM W_RD / Access t W_SRAM W_RD / / /10t /12t Access MSM7630 H_D t SRAM S_D H_D t SRAM t RD 14/95 ...
Page 15
... D t W_AWR t W_SRAM t SRAM W_WR Access W_WRD t W_SRAM W_WR / / / /10t /12t Access MSM7630 SRAM t W_WRSRAM SRAM t W_WRSRAM 15/95 ...
Page 16
... RAS t W_ACAS t CAS t W_RASCAS 2nt Access (Fast Page Mode column address t S_D t W_RAS t W_ACAS t W_CAS t CAS 2nt Access (Fast Page Mode) MSM7630 t t S_D H_D t W_PREC t RAS t W_CAS t CAS column address H_D S_D H_D t W_PREC ...
Page 17
... RAS t W_ACAS t CAS t W_RASCAS 3nt Access (Fast Page Mode) column address t S_D t W_RAS t W_CAS t t CAS 3nt Access (Fast Page Mode) MSM7630 column address t t S_D H_D t t W_RAS W_PREC t RAS t W_CAS t CAS column address S_D ...
Page 18
... CAS t W_RASCAS 3nt Access (Hyperpage Mode column address t S_D t W_RAS t t W_ACAS W_CAS t t CAS CAS 3nt Access (Hyperpage Mode) MSM7630 S_D t RAS t W_EDO W_CAS t CAS t A column address S_D H_D H_D ...
Page 19
... W_WECAS W_WE 2nt Access (Fast Page Mode column address t W_RAS t t W_CAS W_ACAS t CAS t W_WECAS t t W_WE WE 2nt Access (Fast Page Mode) MSM7630 W_PREC t RAS t W_CAS t CAS t WE column address W_PREC t W_CAS t t ...
Page 20
... Access (Fast Page Mode/Hyperpage Mode) OSC t A row address t RAS t W_ACAS t W_RASCAS t W_WECAS t WE column address t W_RAS t W_CAS t t CAS CAS t W_WE MSM7630 column address W_RAS W_PREC t RAS t W_CAS t t CAS CAS t WE column address W_PREC t RAS ...
Page 21
... A D RAS t CAS WE t OSC CLK CLKA RAS t W_CASRAS t CAS CAS WE OSC ignore ignore t W_RAS t RAS W_CASRAS t t W_CAS CAS 2nt CAS-Before-RAS Refresh ignore ignore t W_RAS RAS t W_CAS 3nt CAS-Before-RAS Refresh MSM7630 t RAS t CAS t RAS t CAS 21/95 ...
Page 22
... Semiconductor t CLK CLKA A D RAS t W_CASRAS CAS WE OSC ignore ignore t W_RAS t RAS t t W_CAS CAS CAS-Before-RAS Self-Refresh MSM7630 t RAS t CAS 22/95 ...
Page 23
... D t W_AAS AS t W_AWR WR Bus Write (When DS bit in the SCR register is "0") t CLKA S_D t t W_AAS W_AS W_ARD t t W_RD RD Bus Read W_AS W_WR WR MSM7630 H_D t W_AAS W_AAS 23/95 ...
Page 24
... W_AAS W_AWR WR Bus Write (When DS bit is "1" and X bit is "1" in the SCR register W_AS W_WR WR t W_DWR W_AS t t W_WR WR t W_DWR MSM7630 W_AAS W_AAS 24/95 ...
Page 25
... CLK t CLKA CLKA t t S_PCS H_PCS PCS t t S_PIOA H_PIOA PIOA t W_PACK PACK PSTB PD t PACK PIBF t PACK POBF t t S_PCS H_PCS t t S_PIOA H_PIOA t W_PACK t t S_PD PRDZ t PACK t PRDZ t PRDZ MSM7630 t t S_PCS H_PCS t t S_PIOA H_PIOA t W_PSTB t H_PD 25/95 ...
Page 26
OSC CLK t CLKA CLKA S_RXD H_RXD RXD Start_bit (= 0) t W_RXD t RTS RTS t OSC CLK t CLKA CLKA t t TXD Start_bit (= 0) TXD t W_TXD t t H_CTS S_CTS CTS ...
Page 27
... Semiconductor CLK t CLKA CLKA t SCLK SCLK General Port Output CLK CLKA UPORT t SCLK t W_SCLK Synchronous Transfer Output t CLKA t UPORT General Port Output MSM7630 t SCLK t W_SCLK t UPORT 27/95 ...
Page 28
... Maintain the pin level on the STBY signal until the CPU has completed its suspend process and clock signal CLKA has stopped. After the STBY signal is released, the CPU will not resume until oscillation has stabilized (1024 t * The RST signal is not necessary for self-refresh DRAM. t RSTSTBY_S Suspend Suspend Process MSM7630 t W_RST t RSTSTBY_H t STBYCLKA Operating Resume Process ) ...
Page 29
... Semiconductor Interrupt Process CLK XO CLKA EXTINT The external interrupt signal EXTINT requests an interrupt to the CPU. The pin level on EXTINT must be maintained until the CPU accepts the interrupt. Also, be sure to clear the interrupt source within the interrupt routine. MSM7630 29/95 ...
Page 30
... The general registers are a set of 32 registers with 32-bit width. Of these registers %r0 to %r3 can be used as general registers, but they do have special functions pre-assigned by the system. Registers %r4 to %r31 can be used freely. Contents are undefined after reset. bit 31 Privileged Registers %PSR %VBA %prPSR %IRR %BPA %PC %nPC Special Register %NOP GR MSM7630 0 30/95 ...
Page 31
... Indicates the CPU core version. Currently fixed to "3". • bit[22] MFU32 (read-only) Indicates whether the 32-bit multiplier unit is present ("1") or not ("0"). This is "0" for the MSM7630. • bit[21] MFU16 (read-only) Indicates whether the 16-bit multiplier unit is present ("1") or not ("0"). This is "1" for the MSM7630. ...
Page 32
... PL is restored to its previous state, its saved value in %prPSR will be restored to %PSR. Alternatively PL can be set to its previous value explicitly by an instruction in the interrupt process routine. However, %PSR is a privileged register, so writes are only permitted in supervisor mode. PL will be set to 15 after reset. MSM7630 32/95 ...
Page 33
... MSM7630 pPL ...
Page 34
... Semiconductor The MSM7630 uses only 6 interrupts of the 16 interrupt levels. bit 2.2.5 BPA: Breakpoint Address (read/write) This read/write register sets and shows the instruction address (byte address) where a breakpoint trap occurred. The lowest 2 bits will always be "0". When EBP of %PSR is "1", a trap will be generated immediately before execution of the instruction at the breakpoint set by this register ...
Page 35
... Also, bit addresses specified for bit test instructions and bit manipulation instructions are shown in the diagram below. bit NOP MSM7630 35/95 ...
Page 36
... Memory addressing is big-endian. The diagrams below show memory data formats for byte data access, half-word data access, and word data access. Byte Data Access bit byte Address n Half-Word Data Access bit 31 half word Address n Word Data Access bit 31 Address 16 15 byte byte n+1 n half word word n MSM7630 byte n+3 0 n+1 0 36/95 ...
Page 37
... The effective address (EA) is obtained by adding the value of any general register %r0-31 specified and a displacement given by the instruction’s immediate value field [reg_S1] + offS 3.3.2 Store Instruction Addressing 1. Base + Displacement The effective address (EA) is obtained by adding the value of any general register %r0-31 specified and a displacement given by the instruction’s immediate value field [reg_S1] + offS MSM7630 37/95 ...
Page 38
... Add with carry Subtract with carry Logical AND Logical OR Exclusive OR Subtract MSB extend MSB extend Logical shift Logical rotate Logical shift Arithmetic shift Set bit to "0" Set bit to "1" Invert bit Set bit to "0" Set bit to "1" MSM7630 Function 38/95 ...
Page 39
... S1,S2/immS,D' mulu0 S1,S2/immS,D' mulu16 S1,S2/immS,D' mulu32 S1,S2/immS,D' Multiply instructions need two clocks for execution time. The MSM7630 can only use the mul0 and mulu0 instructions of the multiplication instructions. Instruction Move Move upper bits Store immediate value Store immediate value to upper 16 bits ...
Page 40
... VBA+0x2d0 45 13 VBA+0x2e0 12 46 VBA+0x2f0 11 47 VBA+0x300 10 48 VBA+0x000 VBA+0xff0 to 255 MSM7630 (Sense) Asynchronous (level) Asynchronous (edge) Synchronous Synchronous Synchronous Synchronous Asynchronous (edge) Asynchronous (edge) Synchronous Asynchronous (level) Asynchronous (level) Asynchronous (level) Asynchronous (level) Asynchronous (level) Asynchronous (level) Asynchronous (level) ...
Page 41
... NOP by delayed instruction control (x-bit manipulation), then no exception will be generated. Type: Instruction-synchronous exception caused by an illegal JLR or RT instruction. Vector number/address: Vector number = 2 / VBA+0x020 Conditions: Non-maskable (unconditional). Invalidated by delayed instruction control (x-bit). Saved address: Address of the instruction that caused the exception. PL after interrupt transition: 15 MSM7630 41/95 ...
Page 42
... A data access exception is generated when data is accessed in an undefined memory space. Type: Asynchronous exception caused by a memory access instruction error. Vector number/address: Vector number = 6 / VBA+0x060 Conditions However, exception must be maintained until accepted. Saved address: Address being executed when the exception was accepted. PL after interrupt transition: 15 MSM7630 42/95 ...
Page 43
... Conditions && PL < external_interrupt_number Saved address: Address being executed when the interrupt was accepted. PL after interrupt transition: External interrupt number The MSM7630 assigns interrupt levels as follows. It does not use other interrupts (including NMI). Interrupt Source User Block/TMR2 External pin (EXTINT) ...
Page 44
... EM-bit reset ; delay slot, branch %r1 (old %PC), ; return address not saved ; return to %r2 (old %nPC), %prPSR move to %PSR ; %r2+4 (old %nPC+4)Æ%r1 ; EM-bit reset ; delay slot, branch %r2 (old %nPC), return address not saved ; return to %r1 (old %nPC+4), %prPSR move to %PSR MSM7630 44/95 ...
Page 45
... Reserved 0x3FFFFFFF 0x40000000 General devices 0x7FFFFFFF 0x80000000 Reserved 0xBFFFFFFF 0xC0000000 Internal ROM 0xCFFFFFFF 0xD0000000 Internal RAM 0xDFFFFFFF 0xE0000000 Registers 0xFFFFFFFF ROM 256 MB SRAM 256 MB DRAM 256 256 MB 256 MB 512 MB MSM7630 External 4 GB Internal 45/95 ...
Page 46
... Internal RAM Space Internal RAM space is assigned to 0xD0000000-0xDFFFFFFF used to access internal RAM. This space is not used by the MSM7630. Access to this will cause instruction access exceptions or data access exceptions. 2.7 Register Space Register space is assigned to 0xE0000000-0xFFFFFFFF. Within this space, 0xF8000000-0xFFFFFFFF is assigned for standard I/O and system registers ...
Page 47
... TMR SIO PIO 0xFF000040 0xFF00005F 0xFF000080 0xFF0000FF MSM7630 BSR 0xFF000000 BEA 0xFF000004 ECR 0xFF000008 SCR 0xFF00000C 0xFF000010 0xFF000014 0xFF000018 0xFF00001C 0xFF000020 DRAMC 0xFF00003F System Registers Test Circuit 47/95 ...
Page 48
... These bits provide the source of a bus error. BES = 000 No error BES = 001 BIU register privilege violation BES = 010 Parity error BES = 100 Invalid space access These bits will be "000" after reset. BEA XSP PEB P MSM7630 BES 48/95 ...
Page 49
... Odd parity This bit will be "0" after reset. MSM7630 does not use parity checking ignores this field. • bit[3] A: All Internal ROM (read/write) This bit sets whether or not internal ROM will be accessed instead of external ROM. MSM7630 has no internal ROM, so this bit is always "0". ...
Page 50
... ARW = 101 8t access (7 waits) ARW = 110 10t access (9 waits) ARW = 111 12t access (11 waits) These bits will be "111" after reset AWW AS 0 ORW C D MSM7630 50/95 ...
Page 51
... Ignore parity errors Generate a bus error if a parity error is detected. This bit will be "0" for the MSM7630. • bit[13] OD: ROM Dummy Cycle (read/write) This bit sets whether or not a ROM space access will immediately follow an SRAM space or DRAM space read. ...
Page 52
... PC: Other Parity Check (read/ write) This bit sets parity checking for general device space. It will be "0" after reset Ignore parity errors Generate a bus error if a parity error is detected. This bit will be "0" for the MSM7630. MSM7630 52/95 ...
Page 53
... No general device (space is invalid 8-bit wide device 16-bit wide device 32-bit wide device These bits will be "11" after reset. When this field is "00", attempting to access general device space will cause an instruction access exception or data access exception. MSM7630 53/95 ...
Page 54
... Ignore parity errors Generate a bus error if a parity error is detected. This bit will be "0" for the MSM7630. • bit[25:24] TP: Type (read/write) This bit sets the DRAM’s RAS signal and byte position control signal RAS mode, byte position CAS control ...
Page 55
... These bits will be "00" after reset. • bit[15:13] CA: Column Address (read/write) These bits set the most significant bit position of the column address 000 A08 CA = 001 A09 CA = 010 A10 CA = 011 A11 CA = 100 A12 These bits will be "000" after reset. MSM7630 55/95 ...
Page 56
... CAS-before-RAS self-refresh This bit will be "0" after reset. • bit[9:0] RFC: Refresh Counter (read/write) These bits set the initial value of the refresh counter. It should be set as an integer value obtained by: [(refresh period) (clock period) These bits will be "0000000000" after reset. 16] – 1 MSM7630 56/95 ...
Page 57
... Semiconductor 4. ROM Access The MSM7630 interface with ROM is shown below. ROM MSM7630 The ROM signal will become "0" when the address signal and specified ROM space match. Refer to the timing diagram for basic timing of ROM accesses. 5. SRAM Access The MSM7630 interface with SRAM is shown below. ...
Page 58
... Semiconductor 6. DRAM Access There are two MSM7630 interfaces with DRAM: one when byte position is specified by CAS, and one when byte position is specified by WE. This is set by the DRAM register’s TP field. An interface example when byte position is specified by CAS is shown below. Axx ...
Page 59
... A[10:01] 20-11 10-02 A[11:02] 19-10 09-00 A[09:00] 20-11 10-01 A[10:01] 20-10 09-01 A[11:01] 20-09 08-01 A[12:01] 21-12 11-02 A[11:02] 21-11 10-02 A[12:02] 21-10 09-02 A[13:02] 20-10 09-00 A[10:00] 20-09 08-00 A[11:00] 21-11 10-01 A[11:01] 21-10 09-01 A[12:01] 22-12 11-02 A[12:02] 22-11 10-02 A[13:02] 21-11 10-00 A[10:00] 21-10 09-00 A[11:00] 22-12 11-01 A[11:01] 22-11 10-01 A[12:01] 23-13 12-02 A[12:02] 23-12 11-02 A[13:02] MSM7630 000 01 000 001 01 001 000 00 001 010 01 010 001 00 010 000 01 001 001 01 010 010 01 011 001 10 010 010 10 011 001 01 011 000 00 011 011 10 100 010 01 100 001 00 100 001 10 011 000 01 011 010 10 100 001 01 100 011 ...
Page 60
... Clock synchronized transfer Data length: Transfer sequence: 7 bits or 8 bits selectable LSB first 1 bit or 2 bits selectable No parity, even parity, or odd parity selectable Enables inter-processor communication using the serial port. However, cannot be used together with parity bit. 8 bits fixed LSB first MSM7630 60/95 ...
Page 61
... MSM7630 Flag Flag bit 7 1 bit bit 7 Flag 1 bit 7 ...
Page 62
... A framing error will be detected when a received stop bit is "0". When 2 stop bits have been selected, only the first bit received will be checked. • Overrun errors (start-stop and clock synchronized transfers) An overrun error will be detected when the next receive frame's stop bit is detected before the receive buffer has been read. MSM7630 62/95 ...
Page 63
... DSR) is detected. • Interrupt enable/disable Each interrupt source can be independently enabled or disabled. Also, all interrupts can be disabled at once. • Interrupt requests Whenever any of the five interrupts above is enabled and its conditions are fulfilled, the CPU will get an SIO interrupt request. MSM7630 63/95 ...
Page 64
... This bit can only be written with "0". It will be "0" after reset. • bit[9] SFRE framing error 1 : Framing error generated This bit can only be written with "0". It will be "0" after reset MSM7630 64/95 ...
Page 65
... SRXI receive buffer full interrupt 1 : Receive buffer full interrupt requested This bit is read-only. It will be "0" after reset. • bit[1] STXI transmit buffer empty interrupt 1 : Transmit buffer empty interrupt requested This bit is read-only. It will be "0" after reset. MSM7630 65/95 ...
Page 66
... Receive error interrupts enabled This bit will be "0" after reset. • bit[10] SRXIE 0 : Receive buffer full interrupts disabled 1 : Receive buffer full interrupts enabled This bit will be "0" after reset MSM7630 66/95 ...
Page 67
... This bit will be "0" after reset. • bit[3] SFL 0 : Transfer data length is 8 bits 1 : Transfer data length is 7 bits This bit will be "0" after reset. • bit[2:1] SPTY parity 10 : Even parity 11 : Odd parity These bits will be "00" after reset. MSM7630 67/95 ...
Page 68
... This register provides the states of modem signals. bit • bit[11] DCTS 0 : CTS signal has not changed 1 : CTS signal has changed This bit is read-only. It will be "0" after reset. 0 SBRV MSM7630 68/95 ...
Page 69
... SAEN 0 : Disables auto-enable mode 1 : Enables auto-enable mode This bit will be "0" after reset. • bit[1] RTS 0 : Output RTS signal "0" Output RTS signal "1" This bit will be "0" after reset MSM7630 69/95 ...
Page 70
... This bit will be "0" after reset. 3.8 SCNT: SIO Control Register This register controls SIO. bit • bit[0] CSTP 0 : Enable SIO clock supply 1 : Disable SIO clock supply This bit will be "0" after reset MSM7630 70/95 ...
Page 71
... Semiconductor 4. SIO Register Addresses SIO register addresses for the MSM7630 are shown below. 0xFA000000 0xFA000004 0xFA000008 0xFA00000C 0xFA000010 0xFA000014 0xFA000018 0xFA00001C 5. SIO Operation There are two methods of SIO operation: start-stop transfers where communication is performed synchronized to characters, and clock synchronized transfers where communication is performed synchronized to the clock ...
Page 72
... SCMD’s STEIE and SIEN bits are "1" at this time, then the SSTS’s STEI bit will become "1" and an interrupt request to the CPU will be generated. This interrupt can be released by writing "0" to the SSTS’s STEI bit or the SCMD’s STEIE bit. MSM7630 72/95 ...
Page 73
... P) where B : baud rate f : SCP clock frequency n : baud rate parameter (set by SBR register’s SBRP bit baud rate adjustment value (set by SBR register’s SBRV bit) Set SBR (Baud Rate Adjustment Register) to achieve the required baud rate. MSM7630 73/95 ...
Page 74
... SCMD's STEIE and SIEN bits are "1" at this time, then the SSTS's STEI bit will become "1" and an interrupt request to the CPU will be generated. This interrupt can be released by writing "0" to the SSTS's STEI bit or the SCMD's STEIE or SINT bit. MSM7630 74/95 ...
Page 75
... SSTS's SERI bit will be set to "1" and an interrupt request to the CPU will be generated. 13) To release the interrupt for any error, write "0" to all of SSTS’s SOVE, SFRE, and SPTE bits, or write "0" to SCMD’s SERIE or SIEN bits. MSM7630 75/95 ...
Page 76
... If input buffer full interrupts are enabled, then one will be generated whenever the input buffer is written from an external device. To release input buffer full interrupts, write "0" to the status register PSTS’s PIST bit, to the command register PCMD’s PIIE bit PCMD’s PIEN bit. MSM7630 76/95 ...
Page 77
... This buffer saves data to be output to an external device. It will be undefined after reset. bit 7 0 POB 3.3 PDIR: PIO Direction Register This register specifies under software control whether each parallel port bit is input or output. It will be "00000000" after reset. bit 7 0 PDIR MSM7630 77/95 ...
Page 78
... This bit can only be written with "0". It will be "1" after reset. • bit[1] PSTB strobe 1 : Strobe This bit will be undefined after reset. • bit[0] PIST 0 : Input buffer empty 1 : Input buffer full This bit can only be written with "0". It will be "0" after reset. MSM7630 78/95 ...
Page 79
... Output buffer empty interrupts disabled 1 : Output buffer empty interrupts enabled • bit[0] PIIE 0 : Input buffer full interrupts disabled 1 : Input buffer full interrupts enabled 4. PIO Register Addresses For the MSM7630, PIO register addresses are listed below. 0xFB000000 0xFB000004 0xFB000008 0xFB00000C 0xFB000010 PIO Input Buffer ...
Page 80
... The CPU core verifies that PSTS’s PIST bit is "1" in the PIO interrupt vector process routine and reads the input buffer PIB. It then writes "0" to PSTS’s PIST bit to release the interrupt. 5) When PSTS’s PIST bit becomes "0", the input buffer full output (PIBF) also becomes "0". 6) Repeat the operation from step 2). MSM7630 80/95 ...
Page 81
... PIO interrupt to the CPU core will be generated. This interrupt will be released by writing "0" to PSTS’s POST bit or writing "0" to PCMD’s POIE bit. 6) Write data to the output buffer POB and repeat the operation from step 4). MSM7630 81/95 ...
Page 82
... Repeat the operation from step 2). (B) External operation 1) Read the input buffer full output (PIBF). Chip select input Flag/buffer select input PIOA Read input Write input 2) Verify that the input buffer full output (PIBF) is "0". PCS 0 0 PACK 0 PSTB 1 MSM7630 82/95 ...
Page 83
... Flag/buffer select input PIOA Read input Write input Input/output bus 4) When the output buffer is read, PSTS's POST bit will become "1". 5) Repeat the operation from step 1). PCS 0 1 PACK 1 PSTB 0 PD[7:0] Write data PCS 0 0 PACK 0 PSTB 1 PCS 0 1 PACK 0 PSTB 1 PD[7:0] Read data MSM7630 83/95 ...
Page 84
... This register saves the counter’s initial value. When this register is written, the same value will be written to the Timer Value Register (TCR). This register will be undefined after reset. bit 15 TIR 3.2 TCR: Timer Value Register This register provides the counter’s current value. It will be undefined after reset. bit 15 TCR 0 0 MSM7630 84/95 ...
Page 85
... • bit[7] TCG 0 : Disable timer counter operation 1 : Enable timer counter operation This bit will be "0" after reset. • bit[5] TMOD 0 : Interval timer mode 1 : Divided clock mode This bit will be "0" after reset. MSM7630 85/95 ...
Page 86
... Count clock Count clock Count clock 64 F These bits will be "00" after reset. 4. TMR Register Addresses The MSM7630 has two timers. The register addresses for each are listed below. TMR1 Timer Initial Value Register Timer Value Register Timer Status Register ...
Page 87
... TCAI bit to "0". 5) Set the timer’s initial value in the Timer Initial Value Register TIR. Writing to this register will simultaneously write the same value to the Timer Value Register TCR. 6) Write "1" to TCMR’s TCG bit to start counting and generating a divided clock. MSM7630 87/95 ...
Page 88
... To write data to DAC1 and DAC2, write to DAC2 first, then DAC1. – Do not clear the status register of the TMR2 cleared by an interrupt routine, the sampling frequency for the speech output will change. Interrupt to DATA D WR 12-bit REG 1 MSM7630 CPU TMR2 output 1/2 88/95 ...
Page 89
... This register stores speech output data. It will be "000000000000" after reset. bit DAC1 3.2 DAC2: Speech Output Register 2 This register stores speech output data. It will be "000000000000" after reset. bit DAC2 0x0000 0x0001 0x0001 0x0000 CLK TMR2 output Interrupt to CPU DAC 0 0 MSM7630 0x0002 0x0003 0x0002 89/95 ...
Page 90
... This is a general register. It will be "0" after reset. bit 3.6 MODE7576: MSM7576 Mode Select Register This register sets MSM7576 mode. It will be "0" after reset. bit MSM7630 90/95 ...
Page 91
... DD 2200p 0.1µ – 300p 220p Butterworth low-pass filter R = 47k 4.8 kHz (95 model: for 12 kHz sampling 36k 6.4 kHz (96 model: for 16 kHz sampling 27k 9.6 kHz (97 model: for 22 kHz sampling) MSM7630 6 – 10 – 91/95 ...
Page 92
... Semiconductor Oscillation Circuit There are two methods to generate the MSM7630 system clock: adding an external crystal oscillator or supplying an external clock. 1. Crystal Oscillator The diagram below shows a connection example for a crystal oscillator GND 2. External Clock The diagram below shows an example using an external clock. ...
Page 93
... DSR A18 80 A18 DTR A17 78 A17 A16 CTS 77 A16 RTS A15 76 A15 PD7 A14 75 A14 PD6 A13 74 A13 PD5 A12 73 A12 A11 71 PD4 MSM7630 A11 A10 70 PD3 A10 PD2 PD1 A8 PD0 POBF PIBF A5 PSTB PACK ...
Page 94
... A17 A16 CTS 77 47 A16 RTS A15 76 30 A15 PD7 A14 75 31 A14 A13 74 PD6 33 A13 PD5 A12 73 34 A12 A11 71 PD4 35 MSM7630 A11 A10 70 PD3 36 A10 PD2 PD1 38 A8 PD0 POBF PIBF ...
Page 95
... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM7630 (Unit : mm) Package material Epoxy resin ...