msm7630 Oki Semiconductor, msm7630 Datasheet - Page 87

• Manufacturer Part Number: msm7630
• Description: Universal Speech Processor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
divided clock output value inverts when the counter overflows.
5.2 Divided Clock Mode
In divided clock mode counting begins from the value set in the Timer Initial Value Register, and the
1) Set the TCMR (Command Register) TCG bit to "0", disabling counting.
2) Set TCMR’s TCS bits to select the counter’s increment clock.
3) Set TCMR’s TMOD bit to "1", setting divided clock mode as the operating mode.
4) To generate a periodic divided clock set TCMR’s TCAI bit to "1", which will set the counter to be
5) Set the timer’s initial value in the Timer Initial Value Register TIR. Writing to this register will
6) Write "1" to TCMR’s TCG bit to start counting and generating a divided clock.
loaded with the value of the Timer Initial Value Register each time the counter overflows. For a
one-shot divided clock set the TCAI bit to "0".
simultaneously write the same value to the Timer Value Register TCR.
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