msm7630 Oki Semiconductor, msm7630 Datasheet - Page 72

• Manufacturer Part Number: msm7630
• Description: Universal Speech Processor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
5.1.2 Clock Synchronized Transmit Operation
1) Verify that the SSTS (Status Register) SOST bit is "1", and then write the data to be transferred to
2) Write "0" to SOST to indicate that SOB has valid data.
3) If using SIO interrupts, set the SCMD (Command Register) SIEN bit to "1". If using the transmit
4) If the MCMD (Modem Command Register) SAEN bit is "0", then setting the SCMD (Command
5) SOB (Transmit Buffer) data will be transferred LSB first from the TXD output. Also, a synchronous
6) When the next data can be written to the transmit buffer, the SSTS (Status Register) SOST bit will
7) For continuous transfers, after the SSTS (Status Register) SOST bit becomes "1" write new data to
8) If there is no more data to be transmitted, then write "0" to the SCMD (Command Register) STXIE
9) When transfer of the eighth bit of data ends, the SSTS (Status Register) SOST bit will become "1"
the transmit buffer SOB.
buffer empty interrupt, write "1" to the SCMD STXIE bit. If using the transmit end interrupt, write
"1" to the SCMD STEIE bit.
Register) STEN bit to "1" will start the transfer. If the MCMD SAEN bit is "1", then the transfer will
start when the SCMD STEN bit is "1" and the CTS input is "1".
clock will be transmitted from the SCLK pin. Data on the TXD output will change synchronous
to the falling edge of SCLK. The receiving device should sample TXD data on the rising edge of
SCLK.
change from "0" to "1". If the SCMD (Command Register) STXIE and SIEN bits are "1" at this time,
then the SSTS STXI bit will become "1" and an interrupt request to the CPU will be generated.
SOB (Transmit Buffer) and write "0" to the SOST bit.
bit. This will disable interrupt requests from SIO.
(transmit buffer SOB is empty), SCLK will stop, and the transmit operation will end. If the
SCMD’s STEIE and SIEN bits are "1" at this time, then the SSTS’s STEI bit will become "1" and an
interrupt request to the CPU will be generated. This interrupt can be released by writing "0" to the
SSTS’s STEI bit or the SCMD’s STEIE bit.
MSM7630
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