msm7630 Oki Semiconductor, msm7630 Datasheet - Page 54

• Manufacturer Part Number: msm7630
• Description: Universal Speech Processor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
3.5 DRAM: DRAM Configuration Register
This register sets DRAM space.
After this register has been written, DRAM must not be accessed until the DRAM is operating
properly. Refer to the data sheet of the DRAM used to obtain the required conditions for proper
DRAM operation.
• bit[28:27] DT: Device Type (read/write)
• bit[26] PR: Parity Check (read/write)
• bit[25:24] TP: Type (read/write)
• bit[23] DP: Data Priority (read/write)
bit
These bits set the DRAM device type.
These bits will be "00" after reset.
This bit sets parity checking for DRAM space. It will be "0" after reset.
This bit will be "0" for the MSM7630.
This bit sets the DRAM’s RAS signal and byte position control signal.
These bits will be "00" after reset.
This bit sets the priority of processing when data access is requested by a load/store instruction
during a one-line instruction cache read from DRAM due to an instruction cache miss.
This bit will be "0" after reset.
31
0
0
DT = 00
DT = 01
PR = 0
PR = 1
TP = 00
TP = 01
TP = 10
TP = 11
DP = 0
DP = 1
29
0
28 27 26 25 24
DT
M
E
TP
Fast page mode
Hyperpage mode (EDO DRAM)
Ignore parity errors.
Generate a bus error if a parity error is detected.
1 RAS mode, byte position CAS control
2 RAS mode, byte position CAS control
1 RAS mode, byte position WE control
2 RAS mode, byte position WE control
Give priority to the instruction cache read from DRAM.
Give priority to the data access.
23 22 21 20
D
P MD
RA
18 17 16
CS
15
CA
13 12 11 10 9
SZ
M
R
F
RFC
MSM7630
0
54/95