msm7630 Oki Semiconductor, msm7630 Datasheet - Page 75

• Manufacturer Part Number: msm7630
• Description: Universal Speech Processor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
5.2.3 Start-Stop Receive Operation
1) The receive operation can begin if the MCMD’s SAEN bit is "0" and the SCMD’s SREN bit is "1".
2) If using SIO interrupts, set SCMD’s SIEN bit to "1". If using the receive buffer full interrupt, set
3) The SIO receive operation will start when a falling edge is detected on RXD. The first bit of data
4) When the start bit is received, receive of data will start. If SCMD’s SFL bit is "0", then 8 bits of data
5) When SCMD (Command Register) SFBM bit is "0", a parity bit will be received after the data. The
6) Finally one stop bit will be received. Even if SCMD’s SSTP bit is "1", only the first stop bit will be
7) When all bits have been received, the data input in the receive shift register will be transferred to
8) When data has been transferred from the receive shift register to the receive buffer SIB, SSTS’s SIST
9) When SSTS’s SIST bit is "1" and the SIO enters the state in which data is ready to be transferred
10) If the received stop bit is "0", then it will be considered indication of a framing error. SSTS’s SFRE
11) When SCMD’s SPTY field is "10" or "11", a mismatch between parity generated from the receive
12) If one or more of the SOVE, SFRE, and SPTE bits are "1" and the SCMD' s SERIE and SIEN bits
13) To release the interrupt for any error, write "0" to all of SSTS’s SOVE, SFRE, and SPTE bits, or write
SCMD’s SRXIE bit to "1". If using the receive error interrupt, set SCMD’s SERIE bit to "1".
is received as the start bit. If the received value is "1", then it will not be recognized as a start bit,
the receive operation will be suspended, and the device will wait for another RXD falling edge to
be detected. If the received value is "0", then data will continue to be received.
will be input serially into the receive shift register. If the SFL bit is "1", then 7 bits of data will be
input.
parity will be even if the SPTY field is "10", and odd if the SPTY field is "11". If SCMD’s SFBM bit
is "1" and SPTY is "00", one flag bit will be received. If SCMD’s SFBM bit is "0" and the SPTY field
is "00", then neither a parity bit nor flag bit will be received.
received.
the receive buffer SIB. However, if either of the following two conditions applies, then data will
not be transferred to SIB, and SIB will retain its previous value.
1. SCMD’s SFBM bit is "1", its SPTY field is "00", and the received flag bit does not match SCMD’s
2. An overrun error occurred.
will change from "0" to "1". If SCMD’s SRXIE and SIEN bits are both "1", then SSTS’s SRXI bit will
become "1" and an interrupt request to the CPU will be generated. To release the interrupt, write
"0" to SSTS’s SIST bit or to SCMD’s SRXIE or SIEN bit.
from the receive shift register to the receive buffer, the SIO will assume that an overrun error
(receipt of further data before the value of the receive buffer is read) has occurred. SSTS’s SOVE
bit will then be set to "1".
bit will then be set to "1".
data and the parity bit will be considered a parity error. SSTS’s SPTE bit will then be set to "1".
are "1", then SSTS's SERI bit will be set to "1" and an interrupt request to the CPU will be generated.
"0" to SCMD’s SERIE or SIEN bits.
SFB bit.
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