msm7630 Oki Semiconductor, msm7630 Datasheet - Page 33

• Manufacturer Part Number: msm7630
• Description: Universal Speech Processor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
2.2.2 VBA: Vector Base Address (read/write)
This read/write register sets the leading address of the dispatch table (vector table) to exception,
interrupt, and trap process routines.
The dispatch table is 256 entries of 4K bytes size, with 16 bytes (4 instructions) save for each entry’s
dispatch routine. Entry points are generated by an OR operation with this register, so they are set
at 4K-byte boundaries. As a result, only the upper 20 bits of an argument will be written to the VBA
register (the lower 12 bits will be ignored).
This register is undefined after reset.
2.2.3 prPSR: Pre-Processor Status Register (read/write)
This read/write register saves the value of %PSR at the time an exception, interrupt, or trap is
accepted. In order to accept overlapping exceptions, interrupts, and traps, the value of %prPSR must
be pushed on a stack and then EM of %PSR must be set to "1".
The upper 16 bits of %prPSR are always identical to %PSR. Refer to the descriptions of the same bit
positions in %PSR for an explanation of %prPSR bits.
2.2.4 IRR: Interrupt Request Register (read-only)
This register indicates whether there is an interrupt request at each of the 16 levels of external
interrupts. It is read-only, and shows interrupt requests regardless of PL (processor level). The IRR
value will continue until an interrupt source is released.
bit
bit
bit
31
31
31
0 0 0 0
VER
Entry_point = VBA[31:12] ÍÍ(vector_number << 4)
28 27 26 25 24
0 0 0 0
0 0 0 0
23 22 21 20
0
0 0 0 0
32
M
U
F
VBA
16
M
U
F
0
19 18 17 16
0 0 0 0
0 0 0 0
16
15 14 13 12
15
M
V
N
p
I
14
15
C
R
Q
p
I
13
14
N
R
Q
p
I
12 11
12 11
13
R
Q
p
Z
I
11 10 9 8
12
R
Q
0 0 0 0
0
I
10
11
C
P
R
Q
p
I
I
10
R
Q
p
C
L
9
I
I
N
O
R
Q
p
P
8
9
I
R
Q
0 0
7 6 5 4
0 0
7
8
I
R
Q
6
7
I
R
Q
0 0 0 0 0 0
p
E
B
P
5
6
I
M
R
Q
p
E
4
5
I
R
Q
3
3
4
I
R
Q
2
3
pPL
I
R
Q
1
2
I
MSM7630
R
Q
0
0
0
1
I
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