msm7630 Oki Semiconductor, msm7630 Datasheet - Page 73

• Manufacturer Part Number: msm7630
• Description: Universal Speech Processor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
5.1.3 Clock Synchronized Receive Operation
1) The receive operation will begin if the MCMD’s SAEN bit is "0" (auto-enable mode disabled) and
2) When the receive operation begins, a synchronous clock will be output from SCLK.
3) If using SIO interrupts, set SCMD’s SIEN bit to "1". If using the receive buffer full interrupt, set
4) The transmitting device should input the data to be transferred on RXD on the falling edge of
5) When the eighth bit of data has been received, the receive shift register’s data is transferred to SIB.
6) After data has transferred from the receive shift register to the receive buffer SIB, SIST will change
7) To continue receiving data, read the SIB data after SIS becomes "1", and then write "0" to SIST.
8) To end the receive operation, write "0" to SCMD’s SREN bit. At the time "0" is written to SREN,
9) When SSTS’s SIST bit is "1" and the SIO enters the state in which data is ready to be transferred
5.2 Start-Stop Transfers
Start-stop transfer mode is selected by setting the SCMD (Command Register) SMOD bit to "0". In
this mode data is output LSB first from TXD, and input LSB first from RXD.
5.2.1 Start-Stop Transfer Baud Rate
Set SBR (Baud Rate Adjustment Register) to achieve the required baud rate.
the SCMD’s SREN bit is "1" (data receive enabled).
SCMD’s SRXIE bit to "1".
SCLK, LSB first. The SIO will sample RXD data on SCLK’s rising edge, shifting it into the Receive
Shift Register.
However, it will not be transferred to SIB if an overrun error occurs.
from "0" to "1", indicating that there is valid data in the receive buffer SIB. If SCMD’s SRXI bit and
SIEN bit are both "1" at this time, an interrupt request to the CPU will be generated.
data currently being received will be transferred to SIB and the receive operation will end.
from the receive shift register to the receive buffer, the SIO will assume that an overrun error
(receipt of further data before the value of the receive buffer SIB is read) has occurred. SSTS’s SOVE
bit will then be set to "1". In this case the receive shift register value will not be transferred to the
receive buffer SIB. If SCMD’s SERIE bit and SIEN bit are "1", then SSTS's SERI bit will be set to "1"
and an interrupt request to the CPU will be generated. To release the interrupt, write "0" to SSTS’s
SOVE bit or to SCMD’s SERIE or SIEN bit.
B =
where
B : baud rate
f : SCP clock frequency
n : baud rate parameter (set by SBR register’s SBRP bit)
P : baud rate adjustment value (set by SBR register’s SBRV bit)
16 ¥ n ¥ (256 – P)
f
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