msm7630 Oki Semiconductor, msm7630 Datasheet - Page 51

• Manufacturer Part Number: msm7630
• Description: Universal Speech Processor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
• bit[20:18] AWW: SRAM Write Wait (read/write)
• bit[17:16] AS: SRAM Device Size (read/write)
• bit[14] OC: ROM Parity Check (read/write)
• bit[13] OD: ROM Dummy Cycle (read/write)
These bits set the wait count when SRAM space is accessed by a write.
These bits will be "111" after reset.
These bits set the device size of SRAM space.
These bits will be "00" after reset. When this field is "00", attempting to access SRAM space will
cause an instruction access exception or data access exception.
This bit sets parity checking for ROM space. It will be "0" after reset.
This bit will be "0" for the MSM7630.
This bit sets whether or not a ROM space access will immediately follow an SRAM space or DRAM
space read.
This bit will be "1" after reset.
AWW = 000
AWW = 001
AWW = 010
AWW = 011
AWW = 100
AWW = 101
AWW = 110
AWW = 111
AS = 00
AS = 01
AS = 10
AS = 11
OC = 0
OC = 1
OD = 0
OD = 1
2t access (1 wait)
3t access (2 waits)
4t access (3 waits)
5t access (4 waits)
6t access (5 waits)
8t access (7 waits)
10t access (9 waits)
12t access (11 waits)
No SRAM (space is invalid)
8-bit wide device
16-bit wide device
32-bit wide device
Ignore parity errors.
Generate a bus error if a parity error is detected.
Consecutive access enabled.
Force an interval of at least one clock.
MSM7630
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