mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 104

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

Note 1: A software global reset of the entire MT90222/3/4 component can be achieved by simultaneously writing 1s to bits [7:5].
Note 2: Setting bit 8 to a value of 1 requires that bit 0 also be set to a value of 1. See section 6.6
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
15:14
Bit #
Bit #
Bit #
13:0
15:9
2:0
8:7
5:4
3:0
6
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Unused. Read all 0’s.
Value of the Maximum Operational Delay.
Unused. Read all 0’s.
Write 00 for normal operation
Writing a 1 will reset the value of the maximum delay over time register for the selected
IMA Group (see bits 2:0).
Delay register:
11: Maximum Delay over time (see bits 2:0)
10: Current Maximum Delay for an IMA Group (see bits 2:0)
01: Current Minimum Delay for an IMA Group (see bits 2:0)
00: Current Delay for a link (see bits 3:0)
Bits 3:0 are used to specify the physical link number.
Bits 2:0 are used to specify the physical IMA Group number, based on the delay selected
These 3 bits define the size of the external receive memory:
111: Reserved
110: Reserved
101: 2 banks of 512 K x 8 bits
100: 1 bank of 512 K x 8 bits
011: 2 banks of 128 K x 8 bits
010: 1 bank of 128 K x 8 bits
001: 2 banks of 32 K x 8bits
000: 1 bank of 32 K x 8 bits
1, 2 and 3 are used.
0x029A - 0x02A1 (8 reg)
1 register per IMA Group (value in number of cells). For MT90222 only groups 0,
0000
0x02AA
Used to initiate an update of the RX Delay registers based on the link and delay
value to read
0000
0x0299
Defines the external SRAM configuration.
0000
Table 70 - RX Maximum Operational Delay Register
Table 69 - SRAM Control Register (continued)
(1 reg)
(1 reg)
Table 71 - RX Delay Select Register
Zarlink Semiconductor Inc.
MT90222/3/4
104
Description
Description
Description
Data Sheet