mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 118

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address
14:10
Bit #
Offset
1B-1F
(Hex)
6:5
15
9
8
7
1A
Type
R/W
R/W
R/W
R/W
R/W
Type
R/W
R/W
R
Unused. Read 0.
Clock source select
These 4 bits are used to select the source for the TXCK for the link when TXCK and TX
SYNC are defined as outputs:
The valid combinations are:
00000: RXCK0
00010: RXCK2
00100: RXCK4
00110: RXCK6
01000: RXCK8
01010: RXCK10
01100: RXCK12
01110: RXCK14
10000: REFCK0
10010: REFCK2
Clock and sync direction
When 0, TXCK and TXSYNC are outputs.
When 1, TXCK and TXSYNC are inputs.
Remote Loopback
When 1, TXCK, TXSYNC and DSTo come from the RX pins of the same link.
When 0. normal mode.
Link enable
When 0, the TX port is in high impedance mode
When 1, the TX port is active
Data rate:
11: 8.192 Mb/sec.
10: 4.096 Mb/sec.
01: 2.048 Mb/sec
00: 1.544 Mb/sec
Byte #
--- ---
---, 53
MSB,
8 blocks of 32 words (16 bits) from 0x0500 to 0x05FF
Access these locations directly then use transfer
These registers need to be initialized for proper operation.
command to copy to internal memory. For MT90222 only groups 0, 1, 2 and 3 are
ATM
used.
LSB
0x0600 - 0x060F (16 reg)
1 reg. per TX link.
0000
Table 99 - TX IMA ICP Cell Registers (continued)
LSB: Lower 8 bits of the CRC-10. Inserted by the MT90222/3/4
MSB: Not used by MT90222/3/4.
LSB: Not used by MT90222/3/4.
MSB: Not used by MT90222/3/4.
Table 100 - TDM TX Link Control Register
Zarlink Semiconductor Inc.
MT90222/3/4
01111: RXCK15
00111: RXCK7
01101: RXCK13
00001: RXCK1
00011: RXCK3
00101: RXCK5
01001: RXCK9
01011: RXCK11
10001: REFCK1
10011: REFCK3
118
Description
Description
Data Sheet