mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 37

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

In CTC mode, when using the Fixed algorithm, the Stuff event is periodic and will appear in the same IMA frame,
once every 2048 cells, on each link that is part of the IMA Group.
In CTC mode, when using the Adaptive algorithm, the Stuff event will occur at an average rate of once every 2048
cells on each link and may not occur in the same IMA Frame on all the links. The reference link has one Stuff event
every 2048 cells.
In ITC mode, the Stuff event is determined using the adaptive algorithm that relates the level of the internal TX Link
FIFO with that of the TX Link FIFO of the Reference link. The reference link has one Stuff event every 2048 cells.
The state of bits 7 and 15 in the TX IMA Control (0x0321-0x0324) register determines whether a Stuff indication is
generated in the first or first four frames preceding a Stuff event.
2.4.5
The MT90222/3/4 computes the internal TX IMA Data Cell Rate (IDCR) for each IMA Group. The cell rate for the
IMA Group reference link, specified in the TX Group Control Mode (0x0300-0x0307) register, is integrated over a
programmable period of time. The preferred integration period is programmed in the TX IDCR Integration register
and the value is indicated in Table 1.
Alternately, the integration period can be determined using the following equation:
The optimum performance will be reached when selecting an integration period which results in a number of cells
per integration period which is close to an integer number of cells. As example, for a cell rate equivalent to E1
service (30 timeslots per frame with a frame rate of 8 KHz).
IMA Data Cell Rate
NumberofCells = 94.97 = [30bytes
NumberofCells(perperiod) = [CellRate(persecond)] [IntegrationPeriod(insecond)]
T1 ISDN (23 channels)
Table 1 - IDCR Integration Register Value
T1 (24 channels)
E1(30 channels)
TDM Mode
Zarlink Semiconductor Inc.
MT90222/3/4
8KHz/(53bytespercells)] [(
37
TX IDCR Integration
register (50 MHz)
Preferred Value
2
2
2
17
19
20
clocks
clocks
clocks
2
20)
1/(50MHz)]
Data Sheet