mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 27

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

MT90224 Pin Description (continued)
A10,C11,D11,B11
AE8,AD8,AF7,AE
AF5,AE5,AD5,AE
5,V24,W25,Y26,Y
,A11,C12,D12,B1
2,A12,C13,B13,A
14,B14,C14,A15,
P24,R23,T23,U2
7,AD7,AC7,AF6,
4,AF3,AD4,AE3,
23, AB26,AC26,
B7,A7,D8,C8,
B8,D9,C9,B9
A9,C10,B10,
AE12,AC12,
AC24,AE21,
AE20,AE19,
AC11,AD11,
AF10,AE10,
AF11,AE11,
AC18,AD17
AD10,AF9,
AE9,AD9
A16,B16
Pin #
AD13
AF12
AE13
AD6,
AC9
D15
AF2
B15
sr_cs_1, 0
Name
up_r/w
sr_we
up_wr
up_oe
up_cs
up_irq
[18:0]
[15:0]
up_rd
[15:0]
[11:0]
DSTo
up_d
up_a
sr_d
[7:0]
sr_a
or
or
I/O
I/O Static Memory Data Bus. Data Bus to exchange data between the MT90224 and
I/O Processor Data Bus. Data Bus to exchange data between the MT90224 and a local
O Static Memory Address Bus. Address bus on the external static memory.
O Static Memory Read/Not Write. If low, data is written from the MT90224 to the
O Static Memory Chip Select Signal. Active low.
O Processor Interrupt Request. Open drain signal. If this signal is low, the MT90224
O Serial TDM Data Output 15-0. Serial stream which contains transmit data. The
I
I
I
I
Receiver Static Memory Interface Signals
the external static memory. sr_d[7:0] has internal weak pull-downs.
memory. If high, data is read from the memory to the MT90224.
processor.
Processor Address Bus. Used to select the internal registers and memory
locations of the MT90224.
Processor Read/Not Write. Motorola Mode. This is an input signal. If low, data is
written from the processor to the MT90224. If high, data is read from the MT90224 to
the processor.
Processor Not Write (Intel Mode). This is an input signal, active low. If low, data is
written from the processor to the MT90224.
Output enable (Motorola Mode). This is an input signal. This signal should be tied
to GND for Motorola timing mode.
Processor Read (Intel Mode). This is an input signal, active low. If low, data is read
from the MT90224.
Chip Select. This is an active low input signal. If this signal is high, the MT90224
ignores all other signals on its processor bus. If this signal is low, the MT90224
accepts the signals on its processor bus.
signals to the processor that an interrupt condition is pending inside the MT90224.
output is set to high impedance for unused time slots and if the link is not used. It is
aligned with TXCKio and TXSYNCio.
Processor Interface Signals
Zarlink Semiconductor Inc.
TDM Interface Signals
MT90222/3/4
27
Description
Data Sheet