mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 16

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

MT90222 Pin Description (continued)
B17,C17,A18,B
18,D18,C18,A1
AA3,AA4,
AB2,AB1
AA1,Y3
AA26,
AF21,
AA24,
AD20,
9,B19
Pin #
AF17
AD16
AF13
U24,
C23,
V25,
K26,
B24,
G23,
L25,
G26,
C20
D16
A20
A17
RXRingClk
TXSYNCio
TXRingClk
RXSYNCi
Data[7:0]
PLLREF
TXCKio
REFCK
TXRing
TXRing
RXCKi
Name
Sync
[1:0]
[3:0]
[12]
[12]
[12]
[12]
[8]
[4]
[0]
[8]
[4]
[0]
[8]
[4]
[0]
[8]
[4]
[0]
I/O
I/O
I/O
O
O
O
O
I
I
I
I
TDM Interface Transmit Clock 12, 8, 4 and 0. This pin is an input or an output as
selected by the TDM TX Link Control registers. The TXCK source is software
selectable and can be either one of the four RXCK or one of the four REFCK signals
when defined as output. When defined as input, the proper clock signal is provided to
the input pin. The clock polarity is determined by the TDM TX Link Control registers.
These pins have internal weak pull-downs.
Transmit Line Frame Pulse 12, 8, 4 and 0. This pin is an input or an output as
selected by the TDM TX Link Control registers.
It is the frame reference (typically 8 kHz) used as transmit synchronization for the
TDM system interface. When an output, the TXSYNC is generated from the TXCK
signal and is independent from other TXSYNC signals. Two major modes are
available: generic and ST-BUS:
1. For ST-BUS applications, it is a low going pulse (F0), that delimits the 32/64/128
channel frame of the ST-BUS interface at DSTi and DSTo lines.
2. For generic TDM Interfaces, it can be programmed to generate or receive either a
positive or negative pulse polarity that marks the first bit of the TDM system interface.
These pins have internal weak pull-downs.
Receive line Frame Pulse 12, 8, 4 and 0. This is the frame reference (typically
8 kHz) used as receive synchronization for the TDM system interface. Two major
modes are available: generic and ST-BUS:
1. For ST-BUS applications, it is a low going pulse (F0), that delimits the 32/64/128
channel frame of the ST-BUS interface at DSTi and DSTo lines.
2. For generic TDM Interfaces, it can be programmed to accept either a positive or
negative pulse polarity that marks the first bit of the TDM system interface. These pins
have internal weak pull-downs.
TDM Interface Receive Clock 12, 8, 4 and 0. This input line represents the clock for
the receive serial TDM data. The expected frequency value to be received at this input
clock is defined by the user through the RX Link TDM Control register. These pins
have internal weak pull-downs.
Output reference to an external PLL.
Input Reference Clock inputs 3 to 0. Receive the de-jittered transmit clock reference
to be internally routed to the TXCKio transmit clocks. These pins have internal weak
pull-downs.
TDM Ring TX Clock. Clock output signal used to align the TXRingSync and
TXRingData. Should be connected to the RXRingClk input of the next MT90222
device in the Ring. This output is in High Z state if the TDM Ring is not used. NOT 5 V
TOLERANT.
TDM Ring TX Sync. Synchronization output signal used to retrieve data and control
from the bytes on TXRingData. Should be connected to the RXRingSync input of the
next MT90222 device in the Ring. This output is in High Z state if the TDM Ring is not
used. NOT 5 V TOLERANT.
TDM Ring TX Data[7:0]. Data Bus connecting the TX TDM Ring port to the RX TDM
Ring port. Should be connected to the RXRingData inputs of the next MT90222
device in the Ring. These output are in High Z state if the TDM Ring is not used. NOT
5 V TOLERANT.
TDM Ring RX Clock. Clock input signal used to align the RXRingSync and
RXRingData. Should be connected to the TXRingClk input of the previous MT90222
device in the Ring. There is an internal weak pull-down on this input. NOT 5 V
TOLERANT.
Zarlink Semiconductor Inc.
MT90222/3/4
TDM Ring Signals
16
Description
Data Sheet