mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 60

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

4.8
TXCK and TXSYNC can be either input or output signals. When TXCK and TXSYNC are inputs, they are generated
by external circuitry. When TXCK and TXSYNC are outputs, TXCK source is software selectable and can be any of
the RXCK signals or four external REFCK inputs (see Figure 14). The TXSYNC is generated from the TXCK signal.
The RXCK pins are always defined as inputs and the proper signal must be provided to each input.
4.8.1
The RXSYNC signal is used to align the incoming DSTi data to retrieve all the T1 or E1 channels. The RXSYNC
pulse can be present for each TDM frame (8 Khz) or once per Superframe (an integer number of frames, typically
12 or 16). The period and position of the RXSYNC is verified for each receive block independently. A status bit (1
per link) in the RXSYNC Status (0x0730) register is set if the synchronization pulse occurs at an unexpected time
in the frame. The RX block will be re-aligned with this new synchronization pulse.
4.8.2
The TXSYNC signal is used to align the outgoing DSTo data to retrieve all the T1 or E1 channels. When defined as
input, the TXSYNC pulse can be present for each TDM frame (8Khz) or once per Superframe (every 12 or 24 TDM
frames). The period and position of the TXSYNC is verified for each transmit block independently. A status bit (1 per
link) in the TXSYNC Status (0x0633) register is set if the synchronization pulse occurs at an unexpected time in the
frame. The TX block will be re-aligned with this new synchronization pulse.
4.8.3
Two output pins are provided to simplify the external circuitry required when using an external PLL. These two pins,
PLLREF0 and PLLREF1, re-route any of the RXCK signals and drive the primary and secondary reference signals
of a PLL under software control. Refer to Section 8, Application Notes, for examples.
Clocking Options
Verification of the RXSYNC Period
Verification of the TXSYNC Period
Primary and Secondary Reference Signals
Figure 14 - TXCK and TXSYNC Output Pin Source Options
RXCK 0-15
REFCK 0-3
RXCK 0-15
TX Cell FIFO
Cell Delineation
Zarlink Semiconductor Inc.
MT90222/3/4
60
P/S
S/P
PLLREF0
PLLREF1
DSTi
RXCK
RXSYNC
TXSYNC
DSTo
TXCK
Data Sheet