mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 72

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

MT90222/3/4
Data Sheet
Accessing any of the 24-bit counters provides another example. A ready bit is implemented in the Counter Transfer
Command register when the transfer is completed.
When accessing indirect registers specified by the RX Delay Select (0x02AA) or RX Delay Link Number (0x0286)
registers, the value in the indirect registers can be read when the write to the selection register is effectively done
(i.e., 2.5 system clock cycles after the write cycle is completed). There is no additional delay required.
6.3.4
Clearing of Status Bits
The status bits will remain set until cleared by a specific write action from the microprocessor. Status bits are cleared
by overwriting a zero to the corresponding position in the source register. Each input status register has a related
interrupt enable register. When enabled, setting a bit in the interrupt enable register causes an interrupt to occur in
the corresponding status register bit.
6.3.4.1
Toggle Bit
Some registers include a toggle bit. Toggle bits are used to indicate a write action to any internal register has taken
place. Typically, this bit is toggled 2.5 system clock cycles after performing the write action. To use the toggle bit, its
state (either 0 or 1) must be read (polled) and its state is changed (toggled) when a write command is completed.
This bit is particularly useful when the processor clock is much faster than the MT90222/3/4 system clock.
6.4
Cell Preprocessor Block
The ICP Cell is used in the IMA protocol to exchange information to maintain proper operation between the Far End
and the Near End of the IMA group. One byte, the SCI byte, is used to indicate when there is new information to be
processed in the incoming ICP cell and it is monitored by the IMA software to determine when to process an incoming
ICP cell. I the normal mode of operation, the SCCI byte is monitored and an interrupt is generated whenever the
value of the byte had changed. The software has to read most of the bytes of the new ICP cell to determine which
bytes had changed and take appropriate action.
To simplify the monitoring process of the ICP cell, the MT90222/3/4 includes an option to compare, on a per byte by
byte basis, the most recent incoming cell placed in the RX ICP Cell buffer with the previous cell written in the same
buffer. The cells that are placed in the RX cell buffer are selected based on the criteria specified in the RX Cell Type
RAM (0x0100-0x0101) registers. Another option can be selected where bytes 8, 52 and 53 are not compared and
are not reported. (Byte 8 contains the IMA Frame Sequence number. It is used for the IMA Frame State Machine
and is not used by the Link or Group State Machines. Bytes 52 and 53 contain the CRC-10 and are not required by
the user.) The RX Cell Processor can be enabled on a per link basis.
When the new byte is different, a copy of the new byte along with the byte number is put into a dedicated
preprocessor FIFO, accessible via the Processed RX Cell Link FIFO (0x0140 - 0x014F) registers. There is one
preprocessor FIFO (circular buffer) of 64 entries per RX Link. Each FIFO entry is 16 bits wide and the MT90222/3/4
increments automatically the internal pointer to point to the next entry for the next read access. The Least Significant
Byte (bits 7 to 0) contains the newly received byte that was found to be different. Bits 13 to 8 contain the byte position
in the ATM Cell. The numbering scheme goes from byte #1 to byte #53. The bit 14 is used as a flag to indicate the
last byte that was found to be different in the newly received ATM cell that was put in the RX Cell buffer. Bit 15 is
used to indicate if there are more bytes in the FIFO. A value of "0" indicates the last valid byte (the FIFO is empty)
and a value of "1" indicates that there are more bytes to be read. See below for a representation of a word read from
the FIFO.
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