mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 115

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
15:12
Bit #
Bit #
Bit #
15:0
15:0
11
10
8
7
9
6
5
1
2
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
When set to 1, any bit set in the IRQ Link TC Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. Each bit corresponds to 1
link.
Unused. Read all 0’s.
A ’1’ indicates the end of the LODS condition. Cleared by writing a ’0’.
A ’1’ indicates the end of the LIF condition. Cleared by writing a ’0’.
A ’1’ indicates the end of the LCD condition. Cleared by writing a ’0’.
A ’1’ in this bit means that at least one of the IRQ sources from the IMA Group Overflow
Status Register is requesting service. This bit can be cleared only by servicing the source
of the IRQ.
This bit is valid only for the IRQ Link 0 Status register and is reading always a 0 for the
IRQ Link 1-15 Status registers.
A 1 in this bit means that at least one of the Ready bit used to initiate a transfer of a TX
ICP cell for at least 1 of the IMA Group is returned to 1 (meaning that the transfer of the
TX ICP cell is complete) or a frame pulse was detected for an IMA Group. This bit is
cleared by writing a 0 to it.
This bit is valid only for the IRQ Link 0 Status register and is reading always a 0 for the
IRQ Link 1-7 Status registers.
Overflow in the ICP pre-processing RAM. This status bit can be cleared by writing a ’0’ to
it.
ICP Cell with changes received. The link has received an ICP cell which contain one or
more changes in it. This status bit can be cleared by writing a ’0’ to it.
Each bit represents a link. A ’1’ means that the interrupt form the corresponding link is
enabled and that the level of the IRQ pin is low if the corresponding bit in the IRQ Master
Register is set. A’0’ means that the IRQ level is not affected by the corresponding bit.
be active for correct register operation.
0x0434 (1 reg)
1 register to enable interrupts from the links in TC mode. The RxClk signal must
00
0x0435 - 0x0444 (16 reg)
1 Status register per link.
0000
0x0433 (1 reg)
1 register for all 16 links.
0000
Table 94 - IRQ Link TC Overflow Enable Register
Table 93 - IRQ Master Enable Register
Table 95 - IRQ Link Status Registers
Zarlink Semiconductor Inc.
MT90222/3/4
115
Description
Description
Description
Data Sheet