mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 32

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mt90224

Manufacturer Part Number
mt90224
Description
8-port Ima/tc Phy Device
Manufacturer
Zarlink Semiconductor
Datasheet
1.1.6
Software implements most of the performance monitoring. The MT90222/3/4 provides status information for:
It also provides the content for received ICP cells that contain some changes. The external T1/E1/J1/DSL framers
provide the low level status of the link. The software integrates and responds to the various events.
1.2
The MT90222/3/4 circuitry implements the following functions:
The MT90222/3/4 can be separated into four major independent blocks and five support blocks.The four major
independent blocks are:
the Cell Delineation Block and IMA Frame State Machine
the number of ICP violations
the total number of cells
the total number of User cells
the number of idle or discarded cells.
UTOPIA L1 and L2 compatible Interface (8- bit mode wide bus supported with UTOPIA clock of up to
52 MHz and 16- bit wide with UTOPIA clock of up to 33 MHz)
verification of the incoming HEC (optional)
generation of a new HEC byte
transmit scheduler
generation of the TX IMA Data Cell Rate (IDCR) clock
generation and insertion of ICP cells, Filler Cells and Stuff Cells in IMA mode
generation of Idle Cells in TC mode (from on-chip copies of the cell)
flexible serial link (TDM) formatting of the outgoing bytes
retrieval of ATM Cells from the incoming flexible TDM format
cell delineation
retrieval and processing of ICP cells
synchronization of the IMA Frame
management of the internal re-sequencer RX links (when active)
extraction of the RX IDCR
verification of the delays between links
re-sequencing of ATM cells using external Static RAM
various performance monitoring counters
16-bit microprocessor interface (adaptable to Intel or Motorola interfaces)
the ATM Transmit Path
the ATM Receive Path
the TDM Interface
the UTOPIA Interface
Hardware Functions
Performance Monitoring
Zarlink Semiconductor Inc.
MT90222/3/4
32
Data Sheet

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