mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 11

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

Pin Diagram - MT90222
The MT90222 uses a 384 pin PBGA with a 1.0 mm ball pitch.
AA
AB
AC
AD
AE
AF
G
M
W
A
B
C
D
E
F
H
K
L
N
P
R
T
U
V
Y
J
RXSYN
TXCKio
RXCKi
VDD5
VDD5
Ci[12]
VDD5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
26
PD
PD
PD
PD
PD
26
IC
[8]
[8]
DSTi[4]
DSTi[8]
RXCKi
TXSyn
cio[12]
VDD5
VDD5
VDD5
DSTo
VSS
VSS
NC
NC
NC
NC
NC
NC
[12]
NC
[12]
NC
NC
25
PD
PD
PD
PD
PD
25
IC
IC
RXSYN
TXCKio
TXSyn
cio[8]
Ci[4]
DSTi
VSS
VSS
NC
NC
NC
NC
NC
NC
[12]
NC
NC
NC
[12]
NC
NC
NC
NC
24
PD
PD
PD
PD
24
IC
IC
IC
RXSYN
RXCKi
VDD5
DSTo
V3.3
Ci[8]
V3.3
V2.5
V3.3
V2.5
V3.3
VSS
VSS
VSS
23
NC
NC
NC
NC
NC
NC
NC
NC
PD
PD
NC
NC
NC
23
[4]
[8]
V3.3
V3.3
22
NC
NC
NC
PD
NC
22
IC
TXCKio
DSTo
21
NC
NC
NC
PD
NC
21
IC
[4]
[4]
RXSYN
DSTi[0] TXRing-
RXCKi
TXSyn
VDD5
cio[4]
Ci[0]
20
NC
NC
PD
20
[0]
TXRing-
Data[1]
Data[0]
VDD5
Latch
Test2 TXRing-
19
Clk
PD
NC
PD
19
Figure 2 - MT90222 Pinout (Bottom View)
TXRing-
TXRing-
TXRing-
Data[5]
Data[4]
Data[2]
Data[3]
18
NC
PD
PD
PD
18
TXRing-
TXRing-
TXRing-
Data[7]
Data[6]
TXCKio
DSTo
Sync
V2.5
V3.3
17
NC
17
[0]
[0]
sr_cs_1 sr_a[1] sr_a[4]
sr_cs_0 sr_a[0] sr_a[3] sr_a[5] sr_a[8]
TXRing-
RXRing
Data[7]
RXRing
Data[6]
RXRing
Data[5]
TXSyn
VDD5
cio[0]
VSS
VSS
VSS
VSS
VSS
VSS
Zarlink Semiconductor Inc.
16
Clk
16
MT90222/3/4
RXRing
Data[4]
RXRing
Data[3]
RXRing
Data[2]
sr_we
VDD5 RXRing
VSS
VSS
VSS
VSS
VSS
VSS
15
NC
15
Data[1]
RXRing
Data[0]
RXRing
sr_a[2] sr_a[6]
Sync
V3.3
VSS
VSS
VSS
VSS
VSS
VSS
V2.5
14
14
11
or up_rd
RXRing
VDD5
up_oe
up_cs
V2.5
VSS
VSS
VSS
VSS
VSS
VSS
V3.3
Clk
13
13
sr_a[7]
sr_a[9]
up_r/w
up_wr
VDD5 up_a[6] up_a[3] up_a[0]
up_a
up_a
sr_a
VSS
VSS
VSS
VSS
VSS
VSS
[10]
[10]
[11]
12
12
or
up_a[7]
up_a[8] up_a[4] up_a[1]
up_a[9] up_a[5] up_a[2] VDD5
sr_a
sr_a
sr_a
sr_a
VSS
VSS
VSS
VSS
VSS
VSS
[11]
[12]
[14]
[13]
11
11
sr_a
sr_a
sr_a
V3.3
V2.5
[15]
[16]
[17]
10
10
sr_d[0] sr_d[3] sr_d[7]
sr_d[2] sr_d[5]
up_irq
sr_a
sr_d
[18]
[1]
9
9
sr_d[4]
VDD5
up_d
up_d
[14]
[15]
NC
8
8
sr_d[6]
Test3
up_d
up_d
up_d
up_d
TCK
[10]
[11]
[12]
[13]
7
7
up_d[8] up_d[5] up_d[2]
up_d[9] up_d[7]
VDD5 up_d[6] up_d[4] up_d[1]
TDO
V3.3
V3.3
TDI
NC
6
6
TRST
VDD5
TMS
VSS
VSS
5
5
UTxClk
REFCK
ata[10]
ata[14]
Data[0]
Data[9]
ata[13]
Addr[2]
Addr[4]
Reset
URxD
URxD
URxA
ddr[2]
UTxD
Test4
SOC
VSS
VSS
V3.3
URx
V2.5
V3.3
V2.5
V3.3
V3.3
VSS
UTx
UTx
UTx
UTx
NC
NC
[2]
4
4
UTxPar UTxD
REFCK
REFCK
up_d[3] up_d[0]
Data[1]
Data[5]
Data[7]
ata[15]
Data[2]
Data[6]
ata[10]
Addr[3]
ata[11]
URxD
URxD
URxA
ddr[1]
VDD5
UTxD
VDD5
VDD5
URx-
VSS
URx
URx
URx
URx
Clav
CLK
VSS
UTx
UTx
UTx
Enb
UTx
NC
NC
NC
[0]
[3]
3
3
Data Sheet
Data[0]
Data[3]
Data[8]
ata[12]
Data[1]
Data[3]
ata[12]
ata[15]
Addr[1]
REF[1]
VDD5
URxD
URxA
ddr[3]
VDD5
UTxD
ata[8]
UTxD
VDD5
VSS
URx
URx
URx
URx
URx
Clav
VSS
Enb
UTx
UTx
UTx
UTx
PLL
NC
Par
NC
NC
NC
NC
2
2
REFCK
Data[2]
Data[4]
Data[6]
Data[9]
ata[13]
Data[4]
Data[5]
ata[14]
Addr[0]
REF[0]
ata[11]
URxD
VDD5
VDD5
URxA
ddr[0]
URxA
ddr[4]
UTxD
ata[7]
UTxD
UTxD
Test1
URx
URx
URx
URx
SOC
UTx
UTx
UTx
UTx
PLL
NC
NC
NC
Clk
NC
[1]
1
1
AA
AB
AC
AD
AE
AF
C
D
G
H
M
N
R
U
W
A
B
E
F
J
K
L
P
T
V
Y