mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 74

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

6.6
The SRAM decoding block has a feature that allows more efficient external SRAM memory utilization when only 8
or 4 TDM links are used. This is particularly pertinent to the MT90223 and MT90222.
SRAM address decoding is based in part on the link number. Since the MT90223 and MT90222 use only even
numbered links, normal decoding would result in half the memory not being used. The following method describes
how to more fully utilize one external SRAM component rather than using two external SRAM components, thus
achieving the same differential link delay capacity with reduced board space and cost.
With only one external SRAM physically connected, set bit 0 of the SRAM Control (0x0299) register to use two
banks of memory. Additionally, set bit 8 of the same register to remap SRAM Chip Select 1 (
unused address line. This combination of using two logical memory banks with chip select remapping will achieve
the desired efficient use of a single external SRAM component.
7.0
Throughout the following register descriptions, it should be noted that only the registers and register bits
corresponding to available links are meaningful. Registers and register bits corresponding to unavailable links should
be masked or otherwise ignored. The MT90224 has links 0:15. The MT90223 has links 0, 2, 4, 6, 8, 10, 12 and 14.
The MT90222 has links 0, 4, 8, and 12.
Note: For MT90222 groups 0, 1, 2 and 3 should be used.
7.1
0x0008-0x000B
0x0048-0x004B
0x0000-0x0007
0x0040-0x0047
Address
0x0010
0x0012
0x0050
0x0051
0x0052
0x0053
0x0080
0x0086
0x0087
0x0088
0x0089
0x0011
SRAM Decoding for MT90222/223
Register Summary
Register Descriptions:
(Hex)
Access
Type
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Reset Value
X0000000
000X0000
1X000000
00000000
00000000
00000000
(Hex)
00FF
00FF
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Table 6 - Register Summary
Zarlink Semiconductor Inc.
UTOPIA Output Link Address Registers
UTOPIA Input Link Address Registers
UTOPIA Output Group Address Registers
UTOPIA Output Link PHY Enable Registers
UTOPIA Output Group PHY Enable Register
UTOPIA Output User Defined Byte
UTOPIA Input Group Address Registers
UTOPIA Input Link PHY Enable Register
UTOPIA Input Group PHY Enable Register
UTOPIA Input Control Register
UTOPIA Input Parity Error Register
TX Cell RAM Control Register
TX ICP Cell Handler Register
TX IMA Frame Indication Register
TX ICP Cell Interrupt Enable Register
TX IMA Frame Interrupt Enable Register
MT90222/3/4
74
Description
sr_cs_1
) to the normally
Data Sheet