mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 67

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

6.1.4
Accessing (READ) counters is a three step operation. First, the desired counter must be selected by writing to the
Select Counter Register (0x0432). Second, the READ command (’0x00x101’) is written to the Counter Transfer
Command (0x040F) register. This command causes the current three byte count value to be copied from the
specified counter to the two 16 bit-wide Counter Upper Byte (0x0430) and Counter Bytes 2 and 1 Register
(0x0431) registers (note that this value is unchanged until another counter read command is issued). Lastly, the
Counter Upper Byte (0x0430) and Counter Bytes 2 and 1 Register (0x0431) registers are read to obtain the
three byte count value of the selected counter.
Pre-loading (WRITE) a counter is also a three step function. First, the three byte pre-load value is written to the two
16 bit-wide Counter Upper Byte (0x0430) and Counter Bytes 2 and 1 Register (0x0431) registers. Second,
the identification of the counter to be pre-loaded is written to the Select Counter Register (0x0432). Lastly, the
WRITE command (’0x00x001’) is written to the Counter Transfer Command (0x040F) register.
The IRQ enable bit of a counter is set, or reset, by selecting the counter and writing to the appropriate bit of the
Counter Transfer Command (0x040F) register. The value’0x001010’ enables the counter IRQ and ’xxx00010’
disables (masks) it.
6.1.5
An additional mode of operation is available in the counter block where the values of the counters are transferred,
all at the same time, to a series of internal registers. The transfer can be initiated automatically based on an input
signal or following a transfer command under software control. The transfer mode can be disabled to utilize the
counters in the same method as in the MT90220/221.
When the source for the latch command is from the dedicated input pin, the user has the option to use directly this
signal as a latch command or to divide the incoming signal by 8000 before generating the latch command (for
example, using the 8 kHz F0 frame pulse signal to create 1 second intervals). Bits in the Counter Transfer
Command (0x040F) register are defined to support these new features.
The counters are 24 bits wide when operated as in the MT90220/221 (i.e., without the latching option) and are 16
bits wide when the latching feature is enabled. After each latch signal, all the counters are reset to 0 in order to report
the number of events between two latch commands.
Before the latching mode is enabled, the counters may be loaded (or reset), but the software should not write to the
counters after the latching mode is enabled.
Note: The content of the counter for all cells in the Utopia Transmit block for the IMA Group 7 is not reset by the latch
command when the counters are operating in latch mode. The counter will contain a cumulative count of the ATM
cells that were received on the corresponding Utopia port address. This counter is defined by the value 0x0177 in
the Select Counter Register (0x0432).
Access to the Counters
Latching counter mode
Zarlink Semiconductor Inc.
MT90222/3/4
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Data Sheet